6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-19 04:29:21 +00:00
Code Issues Projects Releases Wiki Activity

expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30987 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-10-16 21:10:32 +00:00
parent 93b11f8284
commit 0505be03ad
4 changed files with 44 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -216,8 +216,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
}
break;
case MachineOperand::MO_ExternalSymbol:
assert(0 && "not implemented");
abort();
O << TAI->getGlobalPrefix() << MO.getSymbolName();
break;
case MachineOperand::MO_ConstantPoolIndex:
O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()

15
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -72,6 +72,10 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
setOperationAction(ISD::VASTART, MVT::Other, Custom);
setOperationAction(ISD::VAEND, MVT::Other, Expand);
@ -321,11 +325,14 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
// node so that legalize doesn't hack it.
// If the callee is a GlobalAddress node (quite common, every direct call is)
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
assert(Callee.getValueType() == MVT::i32);
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
// If this is a direct call, pass the chain and the callee.
assert (Callee.Val);

10
lib/Target/ARM/ARMInstrInfo.td
View File

@ -128,8 +128,8 @@ let isReturn = 1 in {
def bx: InstARM<(ops), "bx r14", [(retflag)]>;
}
let Defs = [R0, R1, R2, R3, R14] in {
def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
let noResults = 1, Defs = [R0, R1, R2, R3, R14] in {
def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", []>;
}
def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
@ -286,3 +286,9 @@ def FLDS : InstARM<(ops FPRegs:$dst, IntRegs:$addr),
def FLDD : InstARM<(ops DFPRegs:$dst, IntRegs:$addr),
"fldd $dst, $addr",
[(set DFPRegs:$dst, (load IntRegs:$addr))]>;
def : Pat<(ARMcall tglobaladdr:$dst),
(bl tglobaladdr:$dst)>;
def : Pat<(ARMcall texternalsym:$dst),
(bl texternalsym:$dst)>;

24
test/CodeGen/ARM/longarith.ll Normal file
View File

@ -0,0 +1,24 @@
; RUN: llvm-as < %s | llc -march=arm &&
; RUN: llvm-as < %s | llc -march=arm | grep __ashldi3 &&
; RUN: llvm-as < %s | llc -march=arm | grep __ashrdi3 &&
; RUN: llvm-as < %s | llc -march=arm | grep __lshrdi3
uint %f1(ulong %x, ubyte %y) {
entry:
%a = shl ulong %x, ubyte %y
%b = cast ulong %a to uint
ret uint %b
}
uint %f2(long %x, ubyte %y) {
entry:
%a = shr long %x, ubyte %y
%b = cast long %a to uint
ret uint %b
}
uint %f3(ulong %x, ubyte %y) {
entry:
%a = shr ulong %x, ubyte %y
%b = cast ulong %a to uint
ret uint %b
}