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Minor optimization to allocate R8 registers in a better order.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19289 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-01-05 16:09:16 +00:00
parent 2dcb9688bb
commit 0539313fe5
1 changed files with 7 additions and 1 deletions
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8
lib/Target/X86/X86RegisterInfo.td
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@ -61,7 +61,13 @@ let Namespace = "X86" in {
// top-level register classes. The order specified in the register list is
// implicitly defined to be the register allocation order.
//
def R8 : RegisterClass<i8, 8, [AL, AH, CL, CH, DL, DH, BL, BH]>;
// List AL,CL,DL before AH,CH,DH, as X86 processors often suffer from false
// dependences between upper and lower parts of the register. BL and BH are
// last because they are call clobbered. Both Athlon and P4 chips suffer this
// issue.
def R8 : RegisterClass<i8, 8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
def R16 : RegisterClass<i16, 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
let Methods = [{
iterator allocation_order_end(MachineFunction &MF) const {