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Change RegVT in BitTestBlock and RegsForValue, to contain MVTs,

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instead of EVTs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169851 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Patrik Hagglund 2012-12-11 10:24:48 +00:00
parent 47fd10f2fc
commit 05749cff9b
2 changed files with 12 additions and 13 deletions
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21
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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@ -593,7 +593,7 @@ namespace {
/// getRegisterType member function, however when with physical registers /// getRegisterType member function, however when with physical registers
/// it is necessary to have a separate record of the types. /// it is necessary to have a separate record of the types.
/// ///
SmallVector<EVT, 4> RegVTs; SmallVector<MVT, 4> RegVTs;
/// Regs - This list holds the registers assigned to the values. /// Regs - This list holds the registers assigned to the values.
/// Each legal or promoted value requires one register, and each /// Each legal or promoted value requires one register, and each
@ -604,7 +604,7 @@ namespace {
RegsForValue() {} RegsForValue() {}
RegsForValue(const SmallVector<unsigned, 4> &regs, RegsForValue(const SmallVector<unsigned, 4> &regs,
EVT regvt, EVT valuevt) MVT regvt, EVT valuevt)
: ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
RegsForValue(LLVMContext &Context, const TargetLowering &tli, RegsForValue(LLVMContext &Context, const TargetLowering &tli,
@ -625,7 +625,7 @@ namespace {
/// areValueTypesLegal - Return true if types of all the values are legal. /// areValueTypesLegal - Return true if types of all the values are legal.
bool areValueTypesLegal(const TargetLowering &TLI) { bool areValueTypesLegal(const TargetLowering &TLI) {
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
EVT RegisterVT = RegVTs[Value]; MVT RegisterVT = RegVTs[Value];
if (!TLI.isTypeLegal(RegisterVT)) if (!TLI.isTypeLegal(RegisterVT))
return false; return false;
} }
@ -687,7 +687,7 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
// Copy the legal parts from the registers. // Copy the legal parts from the registers.
EVT ValueVT = ValueVTs[Value]; EVT ValueVT = ValueVTs[Value];
unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
EVT RegisterVT = RegVTs[Value]; MVT RegisterVT = RegVTs[Value];
Parts.resize(NumRegs); Parts.resize(NumRegs);
for (unsigned i = 0; i != NumRegs; ++i) { for (unsigned i = 0; i != NumRegs; ++i) {
@ -772,7 +772,7 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
EVT ValueVT = ValueVTs[Value]; EVT ValueVT = ValueVTs[Value];
unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
EVT RegisterVT = RegVTs[Value]; MVT RegisterVT = RegVTs[Value];
ISD::NodeType ExtendKind = ISD::NodeType ExtendKind =
TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND; TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
@ -840,7 +840,7 @@ void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
EVT RegisterVT = RegVTs[Value]; MVT RegisterVT = RegVTs[Value];
for (unsigned i = 0; i != NumRegs; ++i) { for (unsigned i = 0; i != NumRegs; ++i) {
assert(Reg < Regs.size() && "Mismatch in # registers expected"); assert(Reg < Regs.size() && "Mismatch in # registers expected");
Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
@ -1800,7 +1800,7 @@ void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
unsigned Reg, unsigned Reg,
BitTestCase &B, BitTestCase &B,
MachineBasicBlock *SwitchBB) { MachineBasicBlock *SwitchBB) {
EVT VT = BB.RegVT; MVT VT = BB.RegVT;
SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
Reg, VT); Reg, VT);
SDValue Cmp; SDValue Cmp;
@ -5749,7 +5749,7 @@ static void GetRegistersForValue(SelectionDAG &DAG,
// Try to convert to the first EVT that the reg class contains. If the // Try to convert to the first EVT that the reg class contains. If the
// types are identical size, use a bitcast to convert (e.g. two differing // types are identical size, use a bitcast to convert (e.g. two differing
// vector types). // vector types).
EVT RegVT = *PhysReg.second->vt_begin(); MVT RegVT = *PhysReg.second->vt_begin();
if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
RegVT, OpInfo.CallOperand); RegVT, OpInfo.CallOperand);
@ -5759,8 +5759,7 @@ static void GetRegistersForValue(SelectionDAG &DAG,
// bitcast to the corresponding integer type. This turns an f64 value // bitcast to the corresponding integer type. This turns an f64 value
// into i64, which can be passed with two i32 values on a 32-bit // into i64, which can be passed with two i32 values on a 32-bit
// machine. // machine.
RegVT = EVT::getIntegerVT(Context, RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
OpInfo.ConstraintVT.getSizeInBits());
OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
RegVT, OpInfo.CallOperand); RegVT, OpInfo.CallOperand);
OpInfo.ConstraintVT = RegVT; OpInfo.ConstraintVT = RegVT;
@ -5770,7 +5769,7 @@ static void GetRegistersForValue(SelectionDAG &DAG,
NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
} }
EVT RegVT; MVT RegVT;
EVT ValueVT = OpInfo.ConstraintVT; EVT ValueVT = OpInfo.ConstraintVT;
// If this is a constraint for a specific physical register, like {r17}, // If this is a constraint for a specific physical register, like {r17},

4
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
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@ -262,7 +262,7 @@ private:
struct BitTestBlock { struct BitTestBlock {
BitTestBlock(APInt F, APInt R, const Value* SV, BitTestBlock(APInt F, APInt R, const Value* SV,
unsigned Rg, EVT RgVT, bool E, unsigned Rg, MVT RgVT, bool E,
MachineBasicBlock* P, MachineBasicBlock* D, MachineBasicBlock* P, MachineBasicBlock* D,
const BitTestInfo& C): const BitTestInfo& C):
First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E), First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
@ -271,7 +271,7 @@ private:
APInt Range; APInt Range;
const Value *SValue; const Value *SValue;
unsigned Reg; unsigned Reg;
EVT RegVT; MVT RegVT;
bool Emitted; bool Emitted;
MachineBasicBlock *Parent; MachineBasicBlock *Parent;
MachineBasicBlock *Default; MachineBasicBlock *Default;