6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-14 17:34:41 +00:00
Code Issues Projects Releases Wiki Activity

Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly

Browse Source 
hardfloat case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78237 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2009-08-05 20:15:19 +00:00
parent be0cf7dbc2
commit 058c251d4a
1 changed files with 7 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -1461,21 +1461,17 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
} else {
TargetRegisterClass *RC;
if (FloatABIType == FloatABI::Hard && RegVT == MVT::f32)
if (RegVT == MVT::f32)
RC = ARM::SPRRegisterClass;
else if (FloatABIType == FloatABI::Hard && RegVT == MVT::f64)
else if (RegVT == MVT::f64)
RC = ARM::DPRRegisterClass;
else if (FloatABIType == FloatABI::Hard && RegVT == MVT::v2f64)
else if (RegVT == MVT::v2f64)
RC = ARM::QPRRegisterClass;
else if (AFI->isThumb1OnlyFunction())
RC = ARM::tGPRRegisterClass;
else if (RegVT == MVT::i32)
RC = (AFI->isThumb1OnlyFunction() ?
ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
else
RC = ARM::GPRRegisterClass;
assert((RegVT == MVT::i32 || RegVT == MVT::f32 ||
(FloatABIType == FloatABI::Hard &&
((RegVT == MVT::f64) || (RegVT == MVT::v2f64)))) &&
"RegVT not supported by FORMAL_ARGUMENTS Lowering");
llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
// Transform the arguments in physical registers into virtual ones.
unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);