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synced 2024-08-26 07:29:55 +00:00
Revert 93158. It's breaking quite a few x86_64 tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93185 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -399,14 +399,6 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
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OutMI.setOpcode(X86::MOVZX32rm16);
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lower_subreg32(&OutMI, 0);
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break;
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case X86::MOV16r0:
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OutMI.setOpcode(X86::MOV32r0);
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lower_subreg32(&OutMI, 0);
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break;
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case X86::MOV64r0:
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OutMI.setOpcode(X86::MOV32r0);
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lower_subreg32(&OutMI, 0);
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break;
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}
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}
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@ -1873,6 +1873,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
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unsigned LoReg, HiReg, ClrReg;
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unsigned ClrOpcode, SExtOpcode;
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EVT ClrVT = NVT;
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switch (NVT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("Unsupported VT!");
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case MVT::i8:
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@ -1882,7 +1883,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
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break;
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case MVT::i16:
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LoReg = X86::AX; HiReg = X86::DX;
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ClrOpcode = X86::MOV16r0; ClrReg = X86::DX;
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ClrOpcode = X86::MOV32r0; ClrReg = X86::EDX; ClrVT = MVT::i32;
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SExtOpcode = X86::CWD;
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break;
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case MVT::i32:
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@ -1892,7 +1893,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
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break;
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case MVT::i64:
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LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
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ClrOpcode = X86::MOV64r0;
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ClrOpcode = ~0U; // NOT USED.
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SExtOpcode = X86::CQO;
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break;
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}
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@ -1931,8 +1932,24 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
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SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Flag, InFlag),0);
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} else {
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// Zero out the high part, effectively zero extending the input.
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SDValue ClrNode =
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SDValue(CurDAG->getMachineNode(ClrOpcode, dl, NVT), 0);
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SDValue ClrNode;
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if (NVT.getSimpleVT() == MVT::i64) {
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ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, MVT::i32),
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0);
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// We just did a 32-bit clear, insert it into a 64-bit register to
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// clear the whole 64-bit reg.
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SDValue Zero = CurDAG->getTargetConstant(0, MVT::i64);
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SDValue SubRegNo =
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CurDAG->getTargetConstant(X86::SUBREG_32BIT, MVT::i32);
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ClrNode =
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SDValue(CurDAG->getMachineNode(TargetInstrInfo::SUBREG_TO_REG, dl,
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MVT::i64, Zero, ClrNode, SubRegNo),
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0);
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} else {
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ClrNode = SDValue(CurDAG->getMachineNode(ClrOpcode, dl, ClrVT), 0);
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}
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InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
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ClrNode, InFlag).getValue(1);
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}
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@ -1598,20 +1598,17 @@ def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
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// Alias Instructions
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//===----------------------------------------------------------------------===//
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// We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
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// smaller encoding, but doing so at isel time interferes with rematerialization
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// in the current register allocator. For now, this is rewritten when the
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// instruction is lowered to an MCInst.
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// Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
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// equivalent due to implicit zero-extending, and it sometimes has a smaller
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// encoding.
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// FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
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// when we have a better way to specify isel priority.
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let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
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def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins),
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"",
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[(set GR64:$dst, 0)]>;
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let AddedComplexity = 1 in
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def : Pat<(i64 0),
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(SUBREG_TO_REG (i64 0), (MOV32r0), x86_subreg_32bit)>;
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// Materialize i64 constant where top 32-bits are zero. This could theoretically
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// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
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// that would make it more difficult to rematerialize.
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// Materialize i64 constant where top 32-bits are zero.
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let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
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def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
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"", [(set GR64:$dst, i64immZExt32:$src)]>;
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@ -1019,16 +1019,12 @@ void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
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switch (Opc) {
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default: break;
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case X86::MOV8r0:
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case X86::MOV16r0:
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case X86::MOV32r0:
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case X86::MOV64r0: {
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case X86::MOV32r0: {
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if (!isSafeToClobberEFLAGS(MBB, I)) {
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switch (Opc) {
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default: break;
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case X86::MOV8r0: Opc = X86::MOV8ri; break;
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case X86::MOV16r0: Opc = X86::MOV16ri; break;
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case X86::MOV32r0: Opc = X86::MOV32ri; break;
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case X86::MOV64r0: Opc = X86::MOV64ri; break;
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}
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Clone = false;
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}
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@ -2295,12 +2291,8 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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OpcodeTablePtr = &RegOp2MemOpTable2Addr;
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isTwoAddrFold = true;
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} else if (i == 0) { // If operand 0
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if (MI->getOpcode() == X86::MOV64r0)
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NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
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else if (MI->getOpcode() == X86::MOV32r0)
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if (MI->getOpcode() == X86::MOV32r0)
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NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
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else if (MI->getOpcode() == X86::MOV16r0)
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NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
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else if (MI->getOpcode() == X86::MOV8r0)
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NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
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if (NewMI)
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@ -2568,9 +2560,7 @@ bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
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} else if (OpNum == 0) { // If operand 0
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switch (Opc) {
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case X86::MOV8r0:
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case X86::MOV16r0:
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case X86::MOV32r0:
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case X86::MOV64r0:
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return true;
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default: break;
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}
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@ -3718,21 +3718,18 @@ let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
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def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
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"xor{b}\t$dst, $dst",
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[(set GR8:$dst, 0)]>;
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// We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
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// encoding and avoids a partial-register update sometimes, but doing so
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// at isel time interferes with rematerialization in the current register
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// allocator. For now, this is rewritten when the instruction is lowered
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// to an MCInst.
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def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
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"",
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[(set GR16:$dst, 0)]>, OpSize;
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def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
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"xor{l}\t$dst, $dst",
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[(set GR32:$dst, 0)]>;
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}
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// Use xorl instead of xorw since we don't care about the high 16 bits,
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// it's smaller, and it avoids a partial-register update.
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let AddedComplexity = 1 in
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def : Pat<(i16 0),
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(EXTRACT_SUBREG (MOV32r0), x86_subreg_16bit)>;
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//===----------------------------------------------------------------------===//
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// Thread Local Storage Instructions
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//
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@ -1,4 +1,5 @@
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; RUN: llc < %s -march=x86-64 | grep {xorl %edi, %edi} | count 4
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; XFAIL: *
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; CodeGen should remat the zero instead of spilling it.
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