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TargetCacheInfo has been removed; its only uses were to propagate a constant

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(16) into certain areas of the SPARC V9 back-end. I'm fairly sure the US IIIi's
dcache has 32-byte lines, so I'm not sure where the 16 came from. However, in
the interest of not breaking things any more than they already are, I'm going
to leave the constant alone.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12043 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke
2004-03-01 06:43:29 +00:00
parent 9b3cbdbedb
commit 05b15fb075
12 changed files with 7 additions and 119 deletions
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include/llvm/Target/TargetCacheInfo.h
-66
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@@ -1,66 +0,0 @@
//===-- llvm/Target/TargetCacheInfo.h ---------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// Describes properties of the target cache architecture.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_TARGETCACHEINFO_H
#define LLVM_TARGET_TARGETCACHEINFO_H
#include "Support/DataTypes.h"
namespace llvm {
class TargetMachine;
struct TargetCacheInfo {
const TargetMachine ⌖
TargetCacheInfo(const TargetCacheInfo&); // DO NOT IMPLEMENT
void operator=(const TargetCacheInfo&); // DO NOT IMPLEMENT
protected:
unsigned int numLevels;
std::vector<unsigned short> cacheLineSizes;
std::vector<unsigned int> cacheSizes;
std::vector<unsigned short> cacheAssoc;
public:
TargetCacheInfo(const TargetMachine& tgt) : target(tgt) {
Initialize();
}
virtual ~TargetCacheInfo() {}
// Default parameters are:
// NumLevels = 2
// L1: LineSize 16, Cache Size 32KB, Direct-mapped (assoc = 1)
// L2: LineSize 32, Cache Size 1 MB, 4-way associative
// NOTE: Cache levels are numbered from 1 as above, not from 0.
//
virtual void Initialize (); // subclass to override defaults
unsigned int getNumCacheLevels () const {
return numLevels;
}
unsigned short getCacheLineSize (unsigned level) const {
assert(level <= cacheLineSizes.size() && "Invalid cache level");
return cacheLineSizes[level-1];
}
unsigned int getCacheSize (unsigned level) const {
assert(level <= cacheSizes.size() && "Invalid cache level");
return cacheSizes[level-1];
}
unsigned short getCacheAssoc (unsigned level) const {
assert(level <= cacheAssoc.size() && "Invalid cache level");
return cacheAssoc[level];
}
};
} // End llvm namespace
#endif
include/llvm/Target/TargetMachine.h
-2
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@@ -25,7 +25,6 @@ class TargetJITInfo;
class TargetSchedInfo;
class TargetRegInfo;
class TargetFrameInfo;
class TargetCacheInfo;
class MachineCodeEmitter;
class MRegisterInfo;
class FunctionPassManager;
@@ -75,7 +74,6 @@ public:
virtual const TargetSchedInfo& getSchedInfo() const = 0;
virtual const TargetRegInfo& getRegInfo() const = 0;
virtual const TargetFrameInfo& getFrameInfo() const = 0;
virtual const TargetCacheInfo& getCacheInfo() const = 0;
const TargetData &getTargetData() const { return DataLayout; }
/// getRegisterInfo - If register information is available, return it. If