mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-25 16:29:20 +00:00
Shrink ADDS, ADC, RSB, and SUBS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78776 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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394346ba3a
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05c269c645
@ -45,29 +45,31 @@ namespace {
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uint8_t Imm2Limit; // Limit of immediate field when it's two-address
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unsigned LowRegs1 : 1; // Only possible if low-registers are used
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unsigned LowRegs2 : 1; // Only possible if low-registers are used (2addr)
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unsigned PredCC1 : 1; // 0 - If predicated, cc is on and vice versa.
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unsigned PredCC1 : 2; // 0 - If predicated, cc is on and vice versa.
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// 1 - No cc field.
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// 2 - Always set CPSR.
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unsigned PredCC2 : 1;
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unsigned Special : 1; // Needs to be dealt with specially
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};
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static const ReduceEntry ReduceTable[] = {
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// Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C, S
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{ ARM::t2ADCrr, ARM::tADC, 0, 0, 0, 1, 0, 0,0, 0 },
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// FIXME: t2ADDS variants.
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{ ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0 },
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{ ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0 },
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// Note: immediate scale is 4.
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{ ARM::t2ADDrSPi,ARM::tADDrSPi,0, 8, 0, 1, 0, 1,0, 0 },
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{ ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 1 },
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{ ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 1 },
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{ ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 0 },
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{ ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 1,0, 0 },
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{ ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 1,0, 0 },
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{ ARM::t2CMPzri,ARM::tCMPzi8, 0, 8, 0, 1, 0, 1,0, 0 },
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{ ARM::t2CMPzrr,ARM::tCMPzhir,0, 0, 0, 0, 0, 1,0, 0 },
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{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 2,0, 0 },
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{ ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0 },
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{ ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0 },
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{ ARM::t2CMPzri,ARM::tCMPzi8, 0, 8, 0, 1, 0, 2,0, 0 },
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{ ARM::t2CMPzrr,ARM::tCMPzhir,0, 0, 0, 0, 0, 2,0, 0 },
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{ ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 0 },
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{ ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 0 },
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@ -84,13 +86,16 @@ namespace {
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{ ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 0 },
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// FIXME: T2RSBri immediate must be zero. Also need entry for T2RSBS
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//{ ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 0 },
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{ ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 1 },
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{ ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0 },
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{ ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0 },
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{ ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0 },
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{ ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0 },
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{ ARM::t2SXTBr, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2SXTHr, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0 },
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{ ARM::t2UXTBr, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2UXTHr, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0 },
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@ -133,6 +138,10 @@ namespace {
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/// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
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DenseMap<unsigned, unsigned> ReduceOpcodeMap;
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bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
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bool is2Addr, ARMCC::CondCodes Pred,
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bool LiveCPSR, bool &HasCC, bool &CCDead);
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bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry);
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@ -165,7 +174,15 @@ Thumb2SizeReduce::Thumb2SizeReduce() : MachineFunctionPass(&ID) {
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}
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}
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static bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
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static bool HasImplicitCPSRDef(const TargetInstrDesc &TID) {
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for (const unsigned *Regs = TID.ImplicitDefs; *Regs; ++Regs)
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if (*Regs == ARM::CPSR)
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return true;
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return false;
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}
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bool
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Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
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bool is2Addr, ARMCC::CondCodes Pred,
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bool LiveCPSR, bool &HasCC, bool &CCDead) {
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if ((is2Addr && Entry.PredCC2 == 0) ||
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@ -188,6 +205,16 @@ static bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
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if (HasCC)
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return false;
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}
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} else if ((is2Addr && Entry.PredCC2 == 2) ||
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(!is2Addr && Entry.PredCC1 == 2)) {
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/// Old opcode has an optional def of CPSR.
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if (HasCC)
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return true;
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// If both old opcode does not implicit CPSR def, then it's not ok since
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// these new opcodes CPSR def is not meant to be thrown away. e.g. CMP.
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if (!HasImplicitCPSRDef(MI->getDesc()))
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return false;
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HasCC = true;
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} else {
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// 16-bit instruction does not set CPSR.
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if (HasCC)
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@ -340,6 +367,33 @@ Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
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const TargetInstrDesc &TID = MI->getDesc();
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if (TID.mayLoad() || TID.mayStore())
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return ReduceLoadStore(MBB, MI, Entry);
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unsigned Opc = MI->getOpcode();
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switch (Opc) {
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default: break;
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case ARM::t2ADDSri:
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case ARM::t2ADDSrr: {
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unsigned PredReg = 0;
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if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
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switch (Opc) {
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default: break;
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case ARM::t2ADDSri: {
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if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR))
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return true;
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// fallthrough
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}
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case ARM::t2ADDSrr:
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return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
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}
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}
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break;
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}
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case ARM::t2RSBri:
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case ARM::t2RSBSri:
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if (MI->getOperand(2).getImm() == 0)
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return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
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break;
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}
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return false;
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}
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@ -395,9 +449,9 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
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// Add the 16-bit instruction.
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DebugLoc dl = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Entry.NarrowOpc2));
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MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID);
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MIB.addOperand(MI->getOperand(0));
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if (HasCC)
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if (HasCC && NewTID.hasOptionalDef())
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AddDefaultT1CC(MIB, CCDead);
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// Transfer the rest of operands.
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@ -475,9 +529,9 @@ Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
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// Add the 16-bit instruction.
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DebugLoc dl = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Entry.NarrowOpc1));
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MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID);
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MIB.addOperand(MI->getOperand(0));
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if (HasCC)
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if (HasCC && NewTID.hasOptionalDef())
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AddDefaultT1CC(MIB, CCDead);
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// Transfer the rest of operands.
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@ -485,16 +539,26 @@ Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
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for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
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if (i < NumOps && TID.OpInfo[i].isOptionalDef())
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continue;
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if ((TID.getOpcode() == ARM::t2RSBSri ||
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TID.getOpcode() == ARM::t2RSBri) && i == 2)
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// Skip the zero immediate operand, it's now implicit.
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continue;
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bool isPred = (i < NumOps && TID.OpInfo[i].isPredicate());
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if (SkipPred && isPred)
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continue;
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const MachineOperand &MO = MI->getOperand(i);
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if (Scale > 1 && !isPred && MO.isImm())
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MIB.addImm(MO.getImm() / Scale);
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else
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else {
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if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
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// Skip implicit def of CPSR. Either it's modeled as an optional
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// def now or it's already an implicit def on the new instruction.
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continue;
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MIB.addOperand(MO);
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}
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}
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if (!TID.isPredicable() && NewTID.isPredicable())
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AddDefaultPred(MIB);
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DOUT << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB;
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@ -503,20 +567,28 @@ Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
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return true;
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}
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static bool UpdateCPSRLiveness(MachineInstr &MI, bool LiveCPSR) {
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static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR) {
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bool HasDef = false;
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI.getOperand(i);
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if (!MO.isReg() || MO.isUndef())
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if (!MO.isReg() || MO.isUndef() || MO.isUse())
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continue;
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if (MO.getReg() != ARM::CPSR)
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continue;
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if (MO.isDef()) {
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if (!MO.isDead())
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HasDef = true;
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continue;
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}
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return HasDef || LiveCPSR;
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}
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static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) {
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI.getOperand(i);
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if (!MO.isReg() || MO.isUndef() || MO.isDef())
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continue;
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if (MO.getReg() != ARM::CPSR)
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continue;
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assert(LiveCPSR && "CPSR liveness tracking is wrong!");
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if (MO.isKill()) {
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LiveCPSR = false;
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@ -524,7 +596,7 @@ static bool UpdateCPSRLiveness(MachineInstr &MI, bool LiveCPSR) {
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}
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}
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return HasDef || LiveCPSR;
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return LiveCPSR;
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}
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bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
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@ -546,6 +618,8 @@ bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
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NextMII = next(MII);
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MachineInstr *MI = &*MII;
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LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);
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unsigned Opcode = MI->getOpcode();
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DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode);
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if (OPI != ReduceOpcodeMap.end()) {
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@ -574,7 +648,7 @@ bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
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}
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ProcessNext:
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LiveCPSR = UpdateCPSRLiveness(*MI, LiveCPSR);
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LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR);
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}
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return Modified;
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@ -1,15 +1,21 @@
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep "subs\\.w r" | count 2
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep "adc\\.w r"
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep "sbc\\.w r" | count 2
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
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define i64 @f1(i64 %a, i64 %b) {
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entry:
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; CHECK: f1:
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; CHECK: subs r0, r0, r2
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; CHECK: sbcs r1, r3
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%tmp = sub i64 %a, %b
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ret i64 %tmp
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}
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define i64 @f2(i64 %a, i64 %b) {
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entry:
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; CHECK: f2:
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; CHECK: adds r0, r0, r0
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; CHECK: adcs r1, r1
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; CHECK: subs r0, r0, r2
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; CHECK: sbcs r1, r3
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%tmp1 = shl i64 %a, 1
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%tmp2 = sub i64 %tmp1, %b
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ret i64 %tmp2
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@ -1,32 +1,48 @@
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {adc\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#171\\|#1179666\\|#872428544\\|#1448498774\\|#66846720} | count 5
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
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; 734439407618 = 0x000000ab00000002
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define i64 @f1(i64 %a) {
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; CHECK: f1:
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; CHECK: adds r0, #2
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%tmp = add i64 %a, 734439407618
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ret i64 %tmp
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}
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; 5066626890203138 = 0x0012001200000002
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define i64 @f2(i64 %a) {
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; CHECK: f2:
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; CHECK: adds r0, #2
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%tmp = add i64 %a, 5066626890203138
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ret i64 %tmp
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}
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; 3747052064576897026 = 0x3400340000000002
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define i64 @f3(i64 %a) {
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; CHECK: f3:
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; CHECK: adds r0, #2
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%tmp = add i64 %a, 3747052064576897026
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ret i64 %tmp
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}
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; 6221254862626095106 = 0x5656565600000002
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define i64 @f4(i64 %a) {
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; CHECK: f4:
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; CHECK: adds r0, #2
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%tmp = add i64 %a, 6221254862626095106
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ret i64 %tmp
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}
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; 287104476244869122 = 0x03fc000000000002
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define i64 @f5(i64 %a) {
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; CHECK: f5:
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; CHECK: adds r0, #2
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%tmp = add i64 %a, 287104476244869122
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ret i64 %tmp
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}
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define i64 @f6(i64 %a, i64 %b) {
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; CHECK: f6:
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; CHECK: adds r0, r0, r2
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%tmp = add i64 %a, %b
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ret i64 %tmp
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}
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@ -1,6 +0,0 @@
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {adc\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]*} | count 1
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define i64 @f1(i64 %a, i64 %b) {
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%tmp = add i64 %a, %b
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ret i64 %tmp
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}
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@ -1,31 +1,46 @@
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {adds\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#171\\|#1179666\\|#872428544\\|#1448498774\\|#66846720} | count 5
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
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; 171 = 0x000000ab
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define i64 @f1(i64 %a) {
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; CHECK: f1:
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; CHECK: adds r0, #171
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; CHECK: adc r1, r1, #0
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%tmp = add i64 %a, 171
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ret i64 %tmp
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}
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; 1179666 = 0x00120012
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define i64 @f2(i64 %a) {
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; CHECK: f2:
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; CHECK: adds.w r0, r0, #1179666
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; CHECK: adc r1, r1, #0
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%tmp = add i64 %a, 1179666
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ret i64 %tmp
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}
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; 872428544 = 0x34003400
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define i64 @f3(i64 %a) {
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; CHECK: f3:
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; CHECK: adds.w r0, r0, #872428544
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; CHECK: adc r1, r1, #0
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%tmp = add i64 %a, 872428544
|
||||
ret i64 %tmp
|
||||
}
|
||||
|
||||
; 1448498774 = 0x56565656
|
||||
define i64 @f4(i64 %a) {
|
||||
; CHECK: f4:
|
||||
; CHECK: adds.w r0, r0, #1448498774
|
||||
; CHECK: adc r1, r1, #0
|
||||
%tmp = add i64 %a, 1448498774
|
||||
ret i64 %tmp
|
||||
}
|
||||
|
||||
; 66846720 = 0x03fc0000
|
||||
define i64 @f5(i64 %a) {
|
||||
; CHECK: f5:
|
||||
; CHECK: adds.w r0, r0, #66846720
|
||||
; CHECK: adc r1, r1, #0
|
||||
%tmp = add i64 %a, 66846720
|
||||
ret i64 %tmp
|
||||
}
|
||||
|
@ -1,6 +1,9 @@
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {adds\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
|
||||
|
||||
define i64 @f1(i64 %a, i64 %b) {
|
||||
; CHECK: f1:
|
||||
; CHECK: adds r0, r0, r2
|
||||
; CHECK: adcs r1, r3
|
||||
%tmp = add i64 %a, %b
|
||||
ret i64 %tmp
|
||||
}
|
||||
|
@ -1,6 +1,8 @@
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {rsb\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*#0} | count 1
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
|
||||
|
||||
define i32 @f1(i32 %a) {
|
||||
; CHECK: f1:
|
||||
; CHECK: rsbs r0, r0, #0
|
||||
%tmp = sub i32 0, %a
|
||||
ret i32 %tmp
|
||||
}
|
||||
|
8
test/CodeGen/Thumb2/thumb2-sbc.ll
Normal file
8
test/CodeGen/Thumb2/thumb2-sbc.ll
Normal file
@ -0,0 +1,8 @@
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
|
||||
|
||||
define i64 @f1(i64 %a, i64 %b) {
|
||||
; CHECK: f1:
|
||||
; CHECK: subs r0, r0, r2
|
||||
%tmp = sub i64 %a, %b
|
||||
ret i64 %tmp
|
||||
}
|
@ -1,6 +0,0 @@
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {sbc\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]*} | count 1
|
||||
|
||||
define i64 @f1(i64 %a, i64 %b) {
|
||||
%tmp = sub i64 %a, %b
|
||||
ret i64 %tmp
|
||||
}
|
@ -1,6 +1,9 @@
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {subs\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1
|
||||
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
|
||||
|
||||
define i64 @f1(i64 %a, i64 %b) {
|
||||
; CHECK: f1:
|
||||
; CHECK: subs r0, r0, r2
|
||||
; CHECK: sbcs r1, r3
|
||||
%tmp = sub i64 %a, %b
|
||||
ret i64 %tmp
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user