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Skip over two-address use operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58883 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -633,6 +633,8 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
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void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
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unsigned ImplicitRd,
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unsigned ImplicitRn) {
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const TargetInstrDesc &TID = MI.getDesc();
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// Part of binary is determined by TableGn.
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unsigned Binary = getBinaryCodeForInstr(MI);
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@ -656,6 +658,10 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
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else
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Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
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// If this is a two-address operand, skip it. e.g. LDR_PRE.
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if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
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++OpIdx;
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const MachineOperand &MO2 = MI.getOperand(OpIdx);
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unsigned AM2Opc = (ImplicitRn == ARM::PC)
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? 0 : MI.getOperand(OpIdx+1).getImm();
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@ -689,6 +695,8 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
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void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
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unsigned ImplicitRn) {
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const TargetInstrDesc &TID = MI.getDesc();
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// Part of binary is determined by TableGn.
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unsigned Binary = getBinaryCodeForInstr(MI);
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@ -707,6 +715,10 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
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else
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Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
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// If this is a two-address operand, skip it. e.g. LDRH_POST.
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if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
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++OpIdx;
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const MachineOperand &MO2 = MI.getOperand(OpIdx);
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unsigned AM3Opc = (ImplicitRn == ARM::PC)
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? 0 : MI.getOperand(OpIdx+1).getImm();
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