mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Add appropriate TSFlags to the instructions that must be always extended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174186 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jyotsna Verma
parent
d9f32c20da
commit
05f52eca94
@ -299,101 +299,95 @@ def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
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// These absolute set addressing mode instructions accept immediate as
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// an operand. We have duplicated these patterns to take global address.
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let neverHasSideEffects = 1 in
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let isExtended = 1, opExtendable = 2, neverHasSideEffects = 1,
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validSubTargets = HasV4SubT in {
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def LDrid_abs_setimm_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
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(ins u6Imm:$addr),
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"$dst1 = memd($dst2=#$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memb(Re=#U6)
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let neverHasSideEffects = 1 in
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def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins u6Imm:$addr),
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"$dst1 = memb($dst2=#$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memh(Re=#U6)
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let neverHasSideEffects = 1 in
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def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins u6Imm:$addr),
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"$dst1 = memh($dst2=#$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memub(Re=#U6)
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let neverHasSideEffects = 1 in
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def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins u6Imm:$addr),
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"$dst1 = memub($dst2=#$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memuh(Re=#U6)
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let neverHasSideEffects = 1 in
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def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins u6Imm:$addr),
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"$dst1 = memuh($dst2=#$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memw(Re=#U6)
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let neverHasSideEffects = 1 in
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def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins u6Imm:$addr),
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"$dst1 = memw($dst2=#$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Following patterns are defined for absolute set addressing mode
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// instruction which take global address as operand.
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let neverHasSideEffects = 1 in
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def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
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(ins globaladdress:$addr),
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(ins u0AlwaysExt:$addr),
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"$dst1 = memd($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memb(Re=#U6)
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let neverHasSideEffects = 1 in
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def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins globaladdress:$addr),
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def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins u0AlwaysExt:$addr),
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"$dst1 = memb($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memh(Re=#U6)
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let neverHasSideEffects = 1 in
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def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins globaladdress:$addr),
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def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins u0AlwaysExt:$addr),
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"$dst1 = memh($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memub(Re=#U6)
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let neverHasSideEffects = 1 in
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def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins globaladdress:$addr),
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def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins u0AlwaysExt:$addr),
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"$dst1 = memub($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memuh(Re=#U6)
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let neverHasSideEffects = 1 in
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def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins globaladdress:$addr),
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def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins u0AlwaysExt:$addr),
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"$dst1 = memuh($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memw(Re=#U6)
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let neverHasSideEffects = 1 in
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def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins globaladdress:$addr),
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def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins u0AlwaysExt:$addr),
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"$dst1 = memw($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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}
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// Following patterns are defined for absolute set addressing mode
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// instruction which take global address as operand.
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let isExtended = 1, opExtendable = 2, neverHasSideEffects = 1,
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validSubTargets = HasV4SubT in {
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def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
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(ins globaladdressExt:$addr),
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"$dst1 = memd($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memb(Re=#U6)
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def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins globaladdressExt:$addr),
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"$dst1 = memb($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memh(Re=#U6)
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def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins globaladdressExt:$addr),
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"$dst1 = memh($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memub(Re=#U6)
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def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins globaladdressExt:$addr),
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"$dst1 = memub($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memuh(Re=#U6)
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def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins globaladdressExt:$addr),
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"$dst1 = memuh($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memw(Re=#U6)
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def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins globaladdressExt:$addr),
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"$dst1 = memw($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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}
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// Load doubleword.
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//
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@ -1457,62 +1451,65 @@ def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
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/// last operand.
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///
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// memd(Re=#U6)=Rtt
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// memd(Re=#U)=Rtt
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let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in {
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def STrid_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
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(ins DoubleRegs:$src1, u6Imm:$src2),
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"memd($dst1=#$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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// memb(Re=#U6)=Rs
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def STrib_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, u6Imm:$src2),
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"memb($dst1=#$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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// memh(Re=#U6)=Rs
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def STrih_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, u6Imm:$src2),
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"memh($dst1=#$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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// memw(Re=#U6)=Rs
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def STriw_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, u6Imm:$src2),
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"memw($dst1=#$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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// memd(Re=#U6)=Rtt
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def STrid_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
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(ins DoubleRegs:$src1, globaladdress:$src2),
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(ins DoubleRegs:$src1, u0AlwaysExt:$src2),
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"memd($dst1=##$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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// memb(Re=#U6)=Rs
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def STrib_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, globaladdress:$src2),
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// memb(Re=#U)=Rs
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def STrib_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, u0AlwaysExt:$src2),
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"memb($dst1=##$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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// memh(Re=#U6)=Rs
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def STrih_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, globaladdress:$src2),
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// memh(Re=#U)=Rs
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def STrih_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, u0AlwaysExt:$src2),
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"memh($dst1=##$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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// memw(Re=#U6)=Rs
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def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, globaladdress:$src2),
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// memw(Re=#U)=Rs
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def STriw_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, u0AlwaysExt:$src2),
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"memw($dst1=##$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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}
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// memd(Re=#U)=Rtt
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let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in {
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def STrid_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
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(ins DoubleRegs:$src1, globaladdressExt:$src2),
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"memd($dst1=##$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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// memb(Re=#U)=Rs
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def STrib_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, globaladdressExt:$src2),
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"memb($dst1=##$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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// memh(Re=#U)=Rs
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def STrih_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, globaladdressExt:$src2),
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"memh($dst1=##$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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// memw(Re=#U)=Rs
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def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, globaladdressExt:$src2),
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"memw($dst1=##$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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}
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// multiclass for store instructions with base + register offset addressing
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// mode
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@ -1632,13 +1629,14 @@ def : Pat<(store (i64 DoubleRegs:$src4),
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}
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// memd(Ru<<#u2+#U6)=Rtt
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let AddedComplexity = 10 in
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let isExtended = 1, opExtendable = 2, AddedComplexity = 10,
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validSubTargets = HasV4SubT in
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def STrid_shl_V4 : STInst<(outs),
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(ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, DoubleRegs:$src4),
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(ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, DoubleRegs:$src4),
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"memd($src1<<#$src2+#$src3) = $src4",
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[(store (i64 DoubleRegs:$src4),
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(add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
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u6ImmPred:$src3))]>,
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u0AlwaysExtPred:$src3))]>,
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Requires<[HasV4T]>;
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// memd(Rx++#s4:3)=Rtt
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@ -1719,13 +1717,14 @@ def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
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Requires<[HasV4T]>;
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// memb(Ru<<#u2+#U6)=Rt
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let AddedComplexity = 10 in
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let isExtended = 1, opExtendable = 2, AddedComplexity = 10, isNVStorable = 1,
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validSubTargets = HasV4SubT in
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def STrib_shl_V4 : STInst<(outs),
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(ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
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(ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
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"memb($src1<<#$src2+#$src3) = $src4",
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[(truncstorei8 (i32 IntRegs:$src4),
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(add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
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u6ImmPred:$src3))]>,
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u0AlwaysExtPred:$src3))]>,
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Requires<[HasV4T]>;
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// memb(Rx++#s4:0:circ(Mu))=Rt
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@ -1749,13 +1748,14 @@ def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
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// memh(Ru<<#u2+#U6)=Rt.H
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// memh(Ru<<#u2+#U6)=Rt
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let AddedComplexity = 10 in
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let isExtended = 1, opExtendable = 2, AddedComplexity = 10, isNVStorable = 1,
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validSubTargets = HasV4SubT in
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def STrih_shl_V4 : STInst<(outs),
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(ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
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(ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
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"memh($src1<<#$src2+#$src3) = $src4",
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[(truncstorei16 (i32 IntRegs:$src4),
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(add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
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u6ImmPred:$src3))]>,
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u0AlwaysExtPred:$src3))]>,
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Requires<[HasV4T]>;
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// memh(Rx++#s4:1:circ(Mu))=Rt.H
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@ -1795,13 +1795,14 @@ def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
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Requires<[HasV4T]>;
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// memw(Ru<<#u2+#U6)=Rt
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let AddedComplexity = 10 in
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let isExtended = 1, opExtendable = 2, AddedComplexity = 10, isNVStorable = 1,
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validSubTargets = HasV4SubT in
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def STriw_shl_V4 : STInst<(outs),
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(ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
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(ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
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"memw($src1<<#$src2+#$src3) = $src4",
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[(store (i32 IntRegs:$src4),
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(add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
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u6ImmPred:$src3))]>,
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u0AlwaysExtPred:$src3))]>,
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Requires<[HasV4T]>;
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// memw(Rx++#s4:2)=Rt
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@ -2365,9 +2366,10 @@ mayStore = 1 in {
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}
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// memb(Ru<<#u2+#U6)=Nt.new
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let mayStore = 1, AddedComplexity = 10 in
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let isExtended = 1, opExtendable = 2, mayStore = 1, AddedComplexity = 10,
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isNVStore = 1, validSubTargets = HasV4SubT in
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def STrib_shl_nv_V4 : NVInst_V4<(outs),
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(ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
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(ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
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"memb($src1<<#$src2+#$src3) = $src4.new",
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[]>,
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Requires<[HasV4T]>;
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@ -2447,9 +2449,10 @@ def STb_GP_nv_V4 : NVInst_V4<(outs),
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Requires<[HasV4T]>;
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// memh(Ru<<#u2+#U6)=Nt.new
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let mayStore = 1, AddedComplexity = 10 in
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let isExtended = 1, opExtendable = 2, mayStore = 1, AddedComplexity = 10,
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isNVStore = 1, validSubTargets = HasV4SubT in
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def STrih_shl_nv_V4 : NVInst_V4<(outs),
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(ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
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(ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
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"memh($src1<<#$src2+#$src3) = $src4.new",
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[]>,
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Requires<[HasV4T]>;
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@ -2476,9 +2479,10 @@ def STh_GP_nv_V4 : NVInst_V4<(outs),
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Requires<[HasV4T]>;
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// memw(Ru<<#u2+#U6)=Nt.new
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let mayStore = 1, AddedComplexity = 10 in
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let isExtended = 1, opExtendable = 2, mayStore = 1, AddedComplexity = 10,
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isNVStore = 1, validSubTargets = HasV4SubT in
|
||||
def STriw_shl_nv_V4 : NVInst_V4<(outs),
|
||||
(ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
|
||||
(ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
|
||||
"memw($src1<<#$src2+#$src3) = $src4.new",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
@ -4460,172 +4464,167 @@ defm STrih_ind : ST_indirect_lo<"memh", truncstorei16>;
|
||||
defm STriw_ind : ST_indirect_lo<"memw", store>;
|
||||
|
||||
// Store - absolute addressing mode: These instruction take constant
|
||||
// value as the extended operand
|
||||
// value as the extended operand.
|
||||
multiclass ST_absimm<string OpcStr> {
|
||||
let isPredicable = 1 in
|
||||
let isExtended = 1, opExtendable = 0, isPredicable = 1,
|
||||
validSubTargets = HasV4SubT in
|
||||
def _abs_V4 : STInst2<(outs),
|
||||
(ins u6Imm:$src1, IntRegs:$src2),
|
||||
!strconcat(OpcStr, "(#$src1) = $src2"),
|
||||
(ins u0AlwaysExt:$src1, IntRegs:$src2),
|
||||
!strconcat(OpcStr, "(##$src1) = $src2"),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
let isExtended = 1, opExtendable = 1, isPredicated = 1,
|
||||
validSubTargets = HasV4SubT in {
|
||||
def _abs_cPt_V4 : STInst2<(outs),
|
||||
(ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
|
||||
!strconcat("if ($src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
|
||||
!strconcat("if ($src1)", !strconcat(OpcStr, "(##$src2) = $src3")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def _abs_cNotPt_V4 : STInst2<(outs),
|
||||
(ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
|
||||
!strconcat("if (!$src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
|
||||
!strconcat("if (!$src1)", !strconcat(OpcStr, "(##$src2) = $src3")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def _abs_cdnPt_V4 : STInst2<(outs),
|
||||
(ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
|
||||
!strconcat("if ($src1.new)",
|
||||
!strconcat(OpcStr, "(#$src2) = $src3")),
|
||||
!strconcat(OpcStr, "(##$src2) = $src3")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def _abs_cdnNotPt_V4 : STInst2<(outs),
|
||||
(ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
|
||||
!strconcat("if (!$src1.new)",
|
||||
!strconcat(OpcStr, "(#$src2) = $src3")),
|
||||
!strconcat(OpcStr, "(##$src2) = $src3")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
}
|
||||
|
||||
let isExtended = 1, opExtendable = 0, mayStore = 1, isNVStore = 1,
|
||||
validSubTargets = HasV4SubT in
|
||||
def _abs_nv_V4 : NVInst_V4<(outs),
|
||||
(ins u0AlwaysExt:$src1, IntRegs:$src2),
|
||||
!strconcat(OpcStr, "(##$src1) = $src2.new"),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
def _abs_nv_V4 : STInst2<(outs),
|
||||
(ins u6Imm:$src1, IntRegs:$src2),
|
||||
!strconcat(OpcStr, "(#$src1) = $src2.new"),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def _abs_cPt_nv_V4 : STInst2<(outs),
|
||||
(ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
|
||||
let isExtended = 1, opExtendable = 1, mayStore = 1, isPredicated = 1,
|
||||
isNVStore = 1, validSubTargets = HasV4SubT in {
|
||||
def _abs_cPt_nv_V4 : NVInst_V4<(outs),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
|
||||
!strconcat("if ($src1)",
|
||||
!strconcat(OpcStr, "(#$src2) = $src3.new")),
|
||||
!strconcat(OpcStr, "(##$src2) = $src3.new")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def _abs_cNotPt_nv_V4 : STInst2<(outs),
|
||||
(ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
|
||||
def _abs_cNotPt_nv_V4 : NVInst_V4<(outs),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
|
||||
!strconcat("if (!$src1)",
|
||||
!strconcat(OpcStr, "(#$src2) = $src3.new")),
|
||||
!strconcat(OpcStr, "(##$src2) = $src3.new")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def _abs_cdnPt_nv_V4 : STInst2<(outs),
|
||||
(ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
|
||||
def _abs_cdnPt_nv_V4 : NVInst_V4<(outs),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
|
||||
!strconcat("if ($src1.new)",
|
||||
!strconcat(OpcStr, "(#$src2) = $src3.new")),
|
||||
!strconcat(OpcStr, "(##$src2) = $src3.new")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
|
||||
(ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
|
||||
def _abs_cdnNotPt_nv_V4 : NVInst_V4<(outs),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
|
||||
!strconcat("if (!$src1.new)",
|
||||
!strconcat(OpcStr, "(#$src2) = $src3.new")),
|
||||
!strconcat(OpcStr, "(##$src2) = $src3.new")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
}
|
||||
}
|
||||
|
||||
defm STrib_imm : ST_absimm<"memb">;
|
||||
defm STrih_imm : ST_absimm<"memh">;
|
||||
defm STriw_imm : ST_absimm<"memw">;
|
||||
|
||||
let Predicates = [HasV4T], AddedComplexity = 30 in
|
||||
def : Pat<(truncstorei8 (i32 IntRegs:$src1), u6ImmPred:$src2),
|
||||
(STrib_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
|
||||
let Predicates = [HasV4T], AddedComplexity = 30 in {
|
||||
def : Pat<(truncstorei8 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
|
||||
(STrib_imm_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
|
||||
|
||||
let Predicates = [HasV4T], AddedComplexity = 30 in
|
||||
def : Pat<(truncstorei16 (i32 IntRegs:$src1), u6ImmPred:$src2),
|
||||
(STrih_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
|
||||
|
||||
let Predicates = [HasV4T], AddedComplexity = 30 in
|
||||
def : Pat<(store (i32 IntRegs:$src1), u6ImmPred:$src2),
|
||||
(STriw_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
|
||||
def : Pat<(truncstorei16 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
|
||||
(STrih_imm_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
|
||||
|
||||
def : Pat<(store (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
|
||||
(STriw_imm_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
|
||||
}
|
||||
|
||||
// Load - absolute addressing mode: These instruction take constant
|
||||
// value as the extended operand
|
||||
|
||||
multiclass LD_absimm<string OpcStr> {
|
||||
let isPredicable = 1 in
|
||||
let isExtended = 1, opExtendable = 1, isPredicable = 1,
|
||||
validSubTargets = HasV4SubT in
|
||||
def _abs_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins u6Imm:$src),
|
||||
(ins u0AlwaysExt:$src),
|
||||
!strconcat("$dst = ",
|
||||
!strconcat(OpcStr, "(#$src)")),
|
||||
!strconcat(OpcStr, "(##$src)")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
let isExtended = 1, opExtendable = 2, isPredicated = 1,
|
||||
validSubTargets = HasV4SubT in {
|
||||
def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, u6Imm:$src2),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2),
|
||||
!strconcat("if ($src1) $dst = ",
|
||||
!strconcat(OpcStr, "(#$src2)")),
|
||||
!strconcat(OpcStr, "(##$src2)")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, u6Imm:$src2),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2),
|
||||
!strconcat("if (!$src1) $dst = ",
|
||||
!strconcat(OpcStr, "(#$src2)")),
|
||||
!strconcat(OpcStr, "(##$src2)")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, u6Imm:$src2),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2),
|
||||
!strconcat("if ($src1.new) $dst = ",
|
||||
!strconcat(OpcStr, "(#$src2)")),
|
||||
!strconcat(OpcStr, "(##$src2)")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, u6Imm:$src2),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2),
|
||||
!strconcat("if (!$src1.new) $dst = ",
|
||||
!strconcat(OpcStr, "(#$src2)")),
|
||||
!strconcat(OpcStr, "(##$src2)")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
}
|
||||
}
|
||||
|
||||
defm LDrib_imm : LD_absimm<"memb">;
|
||||
defm LDrib_imm : LD_absimm<"memb">;
|
||||
defm LDriub_imm : LD_absimm<"memub">;
|
||||
defm LDrih_imm : LD_absimm<"memh">;
|
||||
defm LDrih_imm : LD_absimm<"memh">;
|
||||
defm LDriuh_imm : LD_absimm<"memuh">;
|
||||
defm LDriw_imm : LD_absimm<"memw">;
|
||||
defm LDriw_imm : LD_absimm<"memw">;
|
||||
|
||||
let Predicates = [HasV4T], AddedComplexity = 30 in
|
||||
def : Pat<(i32 (load u6ImmPred:$src)),
|
||||
(LDriw_imm_abs_V4 u6ImmPred:$src)>;
|
||||
let Predicates = [HasV4T], AddedComplexity = 30 in {
|
||||
def : Pat<(i32 (load u0AlwaysExtPred:$src)),
|
||||
(LDriw_imm_abs_V4 u0AlwaysExtPred:$src)>;
|
||||
|
||||
let Predicates = [HasV4T], AddedComplexity=30 in
|
||||
def : Pat<(i32 (sextloadi8 u6ImmPred:$src)),
|
||||
(LDrib_imm_abs_V4 u6ImmPred:$src)>;
|
||||
def : Pat<(i32 (sextloadi8 u0AlwaysExtPred:$src)),
|
||||
(LDrib_imm_abs_V4 u0AlwaysExtPred:$src)>;
|
||||
|
||||
let Predicates = [HasV4T], AddedComplexity=30 in
|
||||
def : Pat<(i32 (zextloadi8 u6ImmPred:$src)),
|
||||
(LDriub_imm_abs_V4 u6ImmPred:$src)>;
|
||||
def : Pat<(i32 (zextloadi8 u0AlwaysExtPred:$src)),
|
||||
(LDriub_imm_abs_V4 u0AlwaysExtPred:$src)>;
|
||||
|
||||
let Predicates = [HasV4T], AddedComplexity=30 in
|
||||
def : Pat<(i32 (sextloadi16 u6ImmPred:$src)),
|
||||
(LDrih_imm_abs_V4 u6ImmPred:$src)>;
|
||||
|
||||
let Predicates = [HasV4T], AddedComplexity=30 in
|
||||
def : Pat<(i32 (zextloadi16 u6ImmPred:$src)),
|
||||
(LDriuh_imm_abs_V4 u6ImmPred:$src)>;
|
||||
def : Pat<(i32 (sextloadi16 u0AlwaysExtPred:$src)),
|
||||
(LDrih_imm_abs_V4 u0AlwaysExtPred:$src)>;
|
||||
|
||||
def : Pat<(i32 (zextloadi16 u0AlwaysExtPred:$src)),
|
||||
(LDriuh_imm_abs_V4 u0AlwaysExtPred:$src)>;
|
||||
}
|
||||
|
||||
// Indexed store double word - global address.
|
||||
// memw(Rs+#u6:2)=#S8
|
||||
|
||||
Loading…
Reference in New Issue
Block a user