From 05fc9664018f867b2184589e8a04cc8f056cfa16 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Sat, 13 Sep 2008 01:35:33 +0000 Subject: [PATCH] Revert 56176. All those instruction formats are still needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56180 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMCodeEmitter.cpp | 12 +++++- lib/Target/ARM/ARMInstrFormats.td | 25 +++++++++---- lib/Target/ARM/ARMInstrInfo.h | 30 +++++++++++---- lib/Target/ARM/ARMInstrInfo.td | 62 +++++++++++++++---------------- 4 files changed, 82 insertions(+), 47 deletions(-) diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index 8302d77f1bf..7abb7d2418b 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -343,7 +343,8 @@ unsigned ARMCodeEmitter::getAddrMode1SBit(const MachineInstr &MI, unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI, const TargetInstrDesc &TID, unsigned Binary) { - if ((TID.TSFlags & ARMII::FormMask) == ARMII::Pseudo) + unsigned Format = TID.TSFlags & ARMII::FormMask; + if (Format == ARMII::Pseudo) abort(); // FIXME // Encode S bit if MI modifies CPSR. @@ -358,7 +359,14 @@ unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI, } // Encode first non-shifter register operand if ther is one. - if ((TID.TSFlags & ARMII::FormMask) != ARMII::UnaryFrm) { + bool isUnary = (Format == ARMII::DPRdMisc || + Format == ARMII::DPRdIm || + Format == ARMII::DPRdReg || + Format == ARMII::DPRdSoReg || + Format == ARMII::DPRnIm || + Format == ARMII::DPRnReg || + Format == ARMII::DPRnSoReg); + if (!isUnary) { Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; ++OpIdx; } diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 4bf295a6fca..eae947e4813 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -28,15 +28,26 @@ def MulSMUL : Format<6>; def Branch : Format<7>; def BranchMisc : Format<8>; -def UnaryFrm : Format<9>; -def BinaryFrm : Format<10>; +def DPRdIm : Format<9>; +def DPRdReg : Format<10>; +def DPRdSoReg : Format<11>; +def DPRdMisc : Format<12>; +def DPRnIm : Format<13>; +def DPRnReg : Format<14>; +def DPRnSoReg : Format<15>; +def DPRIm : Format<16>; +def DPRReg : Format<17>; +def DPRSoReg : Format<18>; +def DPRImS : Format<19>; +def DPRRegS : Format<20>; +def DPRSoRegS : Format<21>; -def LdFrm : Format<11>; -def StFrm : Format<12>; +def LdFrm : Format<22>; +def StFrm : Format<23>; -def ArithMisc : Format<13>; -def ThumbFrm : Format<14>; -def VFPFrm : Format<15>; +def ArithMisc : Format<24>; +def ThumbFrm : Format<25>; +def VFPFrm : Format<26>; //===----------------------------------------------------------------------===// diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h index 55f443ad784..0b27bfbcdc0 100644 --- a/lib/Target/ARM/ARMInstrInfo.h +++ b/lib/Target/ARM/ARMInstrInfo.h @@ -82,21 +82,35 @@ namespace ARMII { BranchMisc = 8 << FormShift, // Data Processing instructions - UnaryFrm = 9 << FormShift, - BinaryFrm = 10 << FormShift, + DPRdIm = 9 << FormShift, + DPRdReg = 10 << FormShift, + DPRdSoReg = 11 << FormShift, + DPRdMisc = 12 << FormShift, + + DPRnIm = 13 << FormShift, + DPRnReg = 14 << FormShift, + DPRnSoReg = 15 << FormShift, + + DPRIm = 16 << FormShift, + DPRReg = 17 << FormShift, + DPRSoReg = 18 << FormShift, + + DPRImS = 19 << FormShift, + DPRRegS = 20 << FormShift, + DPRSoRegS = 21 << FormShift, // Load and Store - LdFrm = 11 << FormShift, - StFrm = 12 << FormShift, + LdFrm = 22 << FormShift, + StFrm = 23 << FormShift, // Miscellaneous arithmetic instructions - ArithMisc = 13 << FormShift, + ArithMisc = 24 << FormShift, // Thumb format - ThumbFrm = 14 << FormShift, + ThumbFrm = 25 << FormShift, // VFP format - VPFFrm = 15 << FormShift, + VPFFrm = 26 << FormShift, // Field shifts - such shifts are used to set field while generating // machine instructions. @@ -104,8 +118,10 @@ namespace ARMII { RegRsShift = 8, RegRdShift = 12, RegRnShift = 16, + L_BitShift = 20, S_BitShift = 20, U_BitShift = 23, + IndexShift = 24, I_BitShift = 25 }; } diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 0ab0f9865fb..32d306570e1 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -344,13 +344,13 @@ include "ARMInstrFormats.td" /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a /// binop that produces a value. multiclass AsI1_bin_irs opcod, string opc, PatFrag opnode> { - def ri : AsI1; - def rr : AsI1; - def rs : AsI1; } @@ -359,13 +359,13 @@ multiclass AsI1_bin_irs opcod, string opc, PatFrag opnode> { /// instruction modifies the CSPR register. let Defs = [CPSR] in { multiclass ASI1_bin_s_irs opcod, string opc, PatFrag opnode> { - def ri : AI1; - def rr : AI1; - def rs : AI1; } @@ -376,13 +376,13 @@ multiclass ASI1_bin_s_irs opcod, string opc, PatFrag opnode> { /// a explicit result, only implicitly set CPSR. let Defs = [CPSR] in { multiclass AI1_cmp_irs opcod, string opc, PatFrag opnode> { - def ri : AI1; - def rr : AI1; - def rs : AI1; } @@ -419,13 +419,13 @@ multiclass AI_bin_rrot opcod, string opc, PatFrag opnode> { let Uses = [CPSR] in { multiclass AsXI1_bin_c_irs opcod, string opc, PatFrag opnode> { def ri : AXI1; def rr : AXI1; def rs : AXI1; } } @@ -743,16 +743,16 @@ def STM : AXI4st<0x0, (outs), // Move Instructions. // -def MOVr : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), UnaryFrm, +def MOVr : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdReg, "mov", " $dst, $src", []>; -def MOVs : AsI1<0xD, (outs GPR:$dst), (ins so_reg:$src), UnaryFrm, +def MOVs : AsI1<0xD, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg, "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>; let isReMaterializable = 1 in -def MOVi : AsI1<0xD, (outs GPR:$dst), (ins so_imm:$src), UnaryFrm, +def MOVi : AsI1<0xD, (outs GPR:$dst), (ins so_imm:$src), DPRdIm, "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>; -def MOVrx : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), UnaryFrm, +def MOVrx : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc, "mov", " $dst, $src, rrx", [(set GPR:$dst, (ARMrrx GPR:$src))]>; @@ -760,10 +760,10 @@ def MOVrx : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), UnaryFrm, // due to flag operands. let Defs = [CPSR] in { -def MOVsrl_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), UnaryFrm, +def MOVsrl_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc, "mov", "s $dst, $src, lsr #1", [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>; -def MOVsra_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), UnaryFrm, +def MOVsra_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc, "mov", "s $dst, $src, asr #1", [(set GPR:$dst, (ARMsra_flag GPR:$src))]>; } @@ -823,20 +823,20 @@ defm ADC : AsXI1_bin_c_irs<0x5, "adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>; defm SBC : AsXI1_bin_c_irs<0x6, "sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>; // These don't define reg/reg forms, because they are handled above. -def RSBri : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), BinaryFrm, +def RSBri : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm, "rsb", " $dst, $a, $b", [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>; -def RSBrs : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), BinaryFrm, +def RSBrs : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg, "rsb", " $dst, $a, $b", [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>; // RSB with 's' bit set. let Defs = [CPSR] in { -def RSBSri : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), BinaryFrm, +def RSBSri : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm, "rsb", "s $dst, $a, $b", [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>; -def RSBSrs : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), BinaryFrm, +def RSBSrs : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg, "rsb", "s $dst, $a, $b", [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>; } @@ -844,10 +844,10 @@ def RSBSrs : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), BinaryFrm, // FIXME: Do not allow RSC to be predicated for now. But they can set CPSR. let Uses = [CPSR] in { def RSCri : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s), - BinaryFrm, "rsc${s} $dst, $a, $b", + DPRIm, "rsc${s} $dst, $a, $b", [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>; def RSCrs : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s), - BinaryFrm, "rsc${s} $dst, $a, $b", + DPRSoReg, "rsc${s} $dst, $a, $b", [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>; } @@ -876,12 +876,12 @@ defm ORR : AsI1_bin_irs<0xC, "orr", BinOpFrag<(or node:$LHS, node:$RHS)>>; defm EOR : AsI1_bin_irs<0x1, "eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>; defm BIC : AsI1_bin_irs<0xE, "bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; -def MVNr : AsI1<0xE, (outs GPR:$dst), (ins GPR:$src), UnaryFrm, +def MVNr : AsI1<0xE, (outs GPR:$dst), (ins GPR:$src), DPRdReg, "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>; -def MVNs : AsI1<0xE, (outs GPR:$dst), (ins so_reg:$src), UnaryFrm, +def MVNs : AsI1<0xE, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg, "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>; let isReMaterializable = 1 in -def MVNi : AsI1<0xE, (outs GPR:$dst), (ins so_imm:$imm), UnaryFrm, +def MVNi : AsI1<0xE, (outs GPR:$dst), (ins so_imm:$imm), DPRdIm, "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>; def : ARMPat<(and GPR:$src, so_imm_not:$imm), @@ -1107,17 +1107,17 @@ def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm), // FIXME: should be able to write a pattern for ARMcmov, but can't use // a two-value operand where a dag node expects two operands. :( def MOVCCr : AI<0xD, (outs GPR:$dst), (ins GPR:$false, GPR:$true), - UnaryFrm, "mov", " $dst, $true", + DPRdReg, "mov", " $dst, $true", [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, RegConstraint<"$false = $dst">; def MOVCCs : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_reg:$true), - UnaryFrm, "mov", " $dst, $true", + DPRdSoReg, "mov", " $dst, $true", [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>, RegConstraint<"$false = $dst">; def MOVCCi : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_imm:$true), - UnaryFrm, "mov", " $dst, $true", + DPRdIm, "mov", " $dst, $true", [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>, RegConstraint<"$false = $dst">; @@ -1165,7 +1165,7 @@ def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), // Two piece so_imms. let isReMaterializable = 1 in -def MOVi2pieces : AI1x2<0x0, (outs GPR:$dst), (ins so_imm2part:$src), Pseudo, +def MOVi2pieces : AI1x2<0x0, (outs GPR:$dst), (ins so_imm2part:$src), DPRdMisc, "mov", " $dst, $src", [(set GPR:$dst, so_imm2part:$src)]>;