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TargetPassConfig: confine the MC configuration to TargetMachine.

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Passes prior to instructon selection are now split into separate configurable stages.
Header dependencies are simplified.
The bulk of this diff is simply removal of the silly DisableVerify flags.

Sorry for the target header churn. Attempting to stabilize them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-02-04 02:56:59 +00:00
parent d542265401
commit 061efcfb3e
26 changed files with 200 additions and 192 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
include/llvm/CodeGen/Passes.h
View File

@ -35,18 +35,17 @@ namespace llvm {
/// ///
/// This is an ImmutablePass solely for the purpose of exposing CodeGen options /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
/// to the internals of other CodeGen passes. /// to the internals of other CodeGen passes.
///
/// FIXME: Why are we passing the DisableVerify flags around instead of setting
/// an options in the target machine, like all the other driver options?
class TargetPassConfig : public ImmutablePass { class TargetPassConfig : public ImmutablePass {
protected: protected:
TargetMachine *TM; TargetMachine *TM;
PassManagerBase ± PassManagerBase ±
// Target Pass Options
//
bool DisableVerify; bool DisableVerify;
public: public:
TargetPassConfig(TargetMachine *tm, PassManagerBase &pm, TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
bool DisableVerifyFlag);
// Dummy constructor. // Dummy constructor.
TargetPassConfig(); TargetPassConfig();
@ -59,17 +58,37 @@ public:
return *static_cast<TMC*>(TM); return *static_cast<TMC*>(TM);
} }
const TargetLowering *getTargetLowering() const {
return TM->getTargetLowering();
}
CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); } CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
const TargetLowering *getTargetLowering() const { return TM->getTargetLowering(); } void setDisableVerify(bool disable) { DisableVerify = disable; }
/// Add common target configurable passes that perform LLVM IR to IR
/// transforms following machine independent optimization.
virtual void addIRPasses();
/// Add common passes that perform LLVM IR to IR transforms in preparation for
/// instruction selection.
virtual void addISelPrepare();
/// addInstSelector - This method should install an instruction selector pass,
/// which converts from LLVM code to machine instructions.
virtual bool addInstSelector() {
return true;
}
/// Add the complete, standard set of LLVM CodeGen passes. /// Add the complete, standard set of LLVM CodeGen passes.
/// Fully developed targets will not generally override this. /// Fully developed targets will not generally override this.
virtual bool addCodeGenPasses(MCContext *&OutContext); virtual void addMachinePasses();
protected: protected:
/// Convenient points in the common codegen pass pipeline for inserting /// Methods with trivial inline returns are convenient points in the common
/// passes, and major CodeGen stages that some targets may override. /// codegen pass pipeline where targets may insert passes. Methods with
/// out-of-line standard implementations are major CodeGen stages called by
/// addMachinePasses. Some targets may override major stages when inserting
/// passes is insufficient, but maintaining overriden stages is more work.
/// ///
/// addPreISelPasses - This method should add any "last minute" LLVM->LLVM /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
@ -78,12 +97,6 @@ protected:
return true; return true;
} }
/// addInstSelector - This method should install an instruction selector pass,
/// which converts from LLVM code to machine instructions.
virtual bool addInstSelector() {
return true;
}
/// addPreRegAlloc - This method may be implemented by targets that want to /// addPreRegAlloc - This method may be implemented by targets that want to
/// run passes immediately before register allocation. This should return /// run passes immediately before register allocation. This should return
/// true if -print-machineinstrs should print after these passes. /// true if -print-machineinstrs should print after these passes.

3
include/llvm/Target/TargetMachine.h
View File

@ -286,8 +286,7 @@ protected: // Can only create subclasses.
public: public:
/// createPassConfig - Create a pass configuration object to be used by /// createPassConfig - Create a pass configuration object to be used by
/// addPassToEmitX methods for generating a pipeline of CodeGen passes. /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
bool DisableVerify);
/// addPassesToEmitFile - Add passes to the specified pass manager to get the /// addPassesToEmitFile - Add passes to the specified pass manager to get the
/// specified file emitted. Typically this will involve several steps of code /// specified file emitted. Typically this will involve several steps of code

105
lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -11,18 +11,24 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "llvm/Target/TargetMachine.h" #include "llvm/Transforms/Scalar.h"
#include "llvm/PassManager.h" #include "llvm/PassManager.h"
#include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h" #include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/OwningPtr.h"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/FormattedStream.h" #include "llvm/Support/FormattedStream.h"
@ -30,6 +36,13 @@
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
// Enable or disable FastISel. Both options are needed, because
// FastISel is enabled by default with -fast, and we wish to be
// able to enable or disable fast-isel independently from -O0.
static cl::opt<cl::boolOrDefault>
EnableFastISelOption("fast-isel", cl::Hidden,
cl::desc("Enable the \"fast\" instruction selector"));
static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden, static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden,
cl::desc("Show encoding in .s output")); cl::desc("Show encoding in .s output"));
static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden, static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden,
@ -65,17 +78,84 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
"and that InitializeAllTargetMCs() is being invoked!"); "and that InitializeAllTargetMCs() is being invoked!");
} }
/// Turn exception handling constructs into something the code generators can
/// handle.
static void addPassesToHandleExceptions(TargetMachine *TM,
PassManagerBase &PM) {
switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
case ExceptionHandling::SjLj:
// SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
// Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
// catch info can get misplaced when a selector ends up more than one block
// removed from the parent invoke(s). This could happen when a landing
// pad is shared by multiple invokes and is also a target of a normal
// edge from elsewhere.
PM.add(createSjLjEHPass(TM->getTargetLowering()));
// FALLTHROUGH
case ExceptionHandling::DwarfCFI:
case ExceptionHandling::ARM:
case ExceptionHandling::Win64:
PM.add(createDwarfEHPass(TM));
break;
case ExceptionHandling::None:
PM.add(createLowerInvokePass(TM->getTargetLowering()));
// The lower invoke pass may create unreachable code. Remove it.
PM.add(createUnreachableBlockEliminationPass());
break;
}
}
/// addPassesToX helper drives creation and initialization of TargetPassConfig.
static MCContext *addPassesToGenerateCode(LLVMTargetMachine *TM,
PassManagerBase &PM,
bool DisableVerify) {
// Targets may override createPassConfig to provide a target-specific sublass.
TargetPassConfig *PassConfig = TM->createPassConfig(PM);
// Set PassConfig options provided by TargetMachine.
PassConfig->setDisableVerify(DisableVerify);
PassConfig->addIRPasses();
addPassesToHandleExceptions(TM, PM);
PassConfig->addISelPrepare();
// Install a MachineModuleInfo class, which is an immutable pass that holds
// all the per-module stuff we're generating, including MCContext.
MachineModuleInfo *MMI =
new MachineModuleInfo(*TM->getMCAsmInfo(), *TM->getRegisterInfo(),
&TM->getTargetLowering()->getObjFileLowering());
PM.add(MMI);
MCContext *Context = &MMI->getContext(); // Return the MCContext specifically by-ref.
// Set up a MachineFunction for the rest of CodeGen to work on.
PM.add(new MachineFunctionAnalysis(*TM));
// Enable FastISel with -fast, but allow that to be overridden.
if (EnableFastISelOption == cl::BOU_TRUE ||
(TM->getOptLevel() == CodeGenOpt::None &&
EnableFastISelOption != cl::BOU_FALSE))
TM->setFastISel(true);
// Ask the target for an isel.
if (PassConfig->addInstSelector())
return NULL;
PassConfig->addMachinePasses();
return Context;
}
bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &Out, formatted_raw_ostream &Out,
CodeGenFileType FileType, CodeGenFileType FileType,
bool DisableVerify) { bool DisableVerify) {
// Add common CodeGen passes. // Add common CodeGen passes.
MCContext *Context = 0; MCContext *Context = addPassesToGenerateCode(this, PM, DisableVerify);
TargetPassConfig *PassConfig = createPassConfig(PM, DisableVerify); if (!Context)
PM.add(PassConfig);
if (PassConfig->addCodeGenPasses(Context))
return true; return true;
assert(Context != 0 && "Failed to get MCContext");
if (hasMCSaveTempLabels()) if (hasMCSaveTempLabels())
Context->setAllowTemporaryLabels(false); Context->setAllowTemporaryLabels(false);
@ -156,9 +236,8 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
JITCodeEmitter &JCE, JITCodeEmitter &JCE,
bool DisableVerify) { bool DisableVerify) {
// Add common CodeGen passes. // Add common CodeGen passes.
MCContext *Ctx = 0; MCContext *Context = addPassesToGenerateCode(this, PM, DisableVerify);
OwningPtr<TargetPassConfig> PassConfig(createPassConfig(PM, DisableVerify)); if (!Context)
if (PassConfig->addCodeGenPasses(Ctx))
return true; return true;
addCodeEmitter(PM, JCE); addCodeEmitter(PM, JCE);
@ -177,8 +256,8 @@ bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
raw_ostream &Out, raw_ostream &Out,
bool DisableVerify) { bool DisableVerify) {
// Add common CodeGen passes. // Add common CodeGen passes.
OwningPtr<TargetPassConfig> PassConfig(createPassConfig(PM, DisableVerify)); Ctx = addPassesToGenerateCode(this, PM, DisableVerify);
if (PassConfig->addCodeGenPasses(Ctx)) if (!Ctx)
return true; return true;
if (hasMCSaveTempLabels()) if (hasMCSaveTempLabels())

88
lib/CodeGen/Passes.cpp
View File

@ -17,16 +17,11 @@
#include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Scalar.h"
#include "llvm/PassManager.h" #include "llvm/PassManager.h"
#include "llvm/CodeGen/GCStrategy.h" #include "llvm/CodeGen/GCStrategy.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/Assembly/PrintModulePass.h" #include "llvm/Assembly/PrintModulePass.h"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
@ -77,13 +72,6 @@ static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
cl::desc("Verify generated machine code"), cl::desc("Verify generated machine code"),
cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL)); cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
// Enable or disable FastISel. Both options are needed, because
// FastISel is enabled by default with -fast, and we wish to be
// able to enable or disable fast-isel independently from -O0.
static cl::opt<cl::boolOrDefault>
EnableFastISelOption("fast-isel", cl::Hidden,
cl::desc("Enable the \"fast\" instruction selector"));
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
/// TargetPassConfig /// TargetPassConfig
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
@ -95,9 +83,8 @@ char TargetPassConfig::ID = 0;
// Out of line virtual method. // Out of line virtual method.
TargetPassConfig::~TargetPassConfig() {} TargetPassConfig::~TargetPassConfig() {}
TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm, TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
bool DisableVerifyFlag) : ImmutablePass(ID), TM(tm), PM(pm), DisableVerify(false) {
: ImmutablePass(ID), TM(tm), PM(pm), DisableVerify(DisableVerifyFlag) {
// Register all target independent codegen passes to activate their PassIDs, // Register all target independent codegen passes to activate their PassIDs,
// including this pass itself. // including this pass itself.
initializeCodeGen(*PassRegistry::getPassRegistry()); initializeCodeGen(*PassRegistry::getPassRegistry());
@ -107,9 +94,8 @@ TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm,
/// addPassToEmitX methods for generating a pipeline of CodeGen passes. /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
/// ///
/// Targets may override this to extend TargetPassConfig. /// Targets may override this to extend TargetPassConfig.
TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM, TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
bool DisableVerify) { return new TargetPassConfig(this, PM);
return new TargetPassConfig(this, PM, DisableVerify);
} }
TargetPassConfig::TargetPassConfig() TargetPassConfig::TargetPassConfig()
@ -117,6 +103,9 @@ TargetPassConfig::TargetPassConfig()
llvm_unreachable("TargetPassConfig should not be constructed on-the-fly"); llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
} }
void TargetPassConfig::addCommonPass(char &ID) {
// FIXME: about to be implemented.
}
void TargetPassConfig::printNoVerify(const char *Banner) const { void TargetPassConfig::printNoVerify(const char *Banner) const {
if (TM->shouldPrintMachineCode()) if (TM->shouldPrintMachineCode())
@ -131,12 +120,9 @@ void TargetPassConfig::printAndVerify(const char *Banner) const {
PM.add(createMachineVerifierPass(Banner)); PM.add(createMachineVerifierPass(Banner));
} }
/// addCodeGenPasses - Add standard LLVM codegen passes used for both /// Add common target configurable passes that perform LLVM IR to IR transforms
/// emitting to assembly files or machine code output. /// following machine independent optimization.
/// void TargetPassConfig::addIRPasses() {
bool TargetPassConfig::addCodeGenPasses(MCContext *&OutContext) {
// Standard LLVM-Level Passes.
// Basic AliasAnalysis support. // Basic AliasAnalysis support.
// Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
// BasicAliasAnalysis wins if they disagree. This is intended to help // BasicAliasAnalysis wins if they disagree. This is intended to help
@ -160,32 +146,11 @@ bool TargetPassConfig::addCodeGenPasses(MCContext *&OutContext) {
// Make sure that no unreachable blocks are instruction selected. // Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass()); PM.add(createUnreachableBlockEliminationPass());
// Turn exception handling constructs into something the code generators can
// handle.
switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
case ExceptionHandling::SjLj:
// SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
// Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
// catch info can get misplaced when a selector ends up more than one block
// removed from the parent invoke(s). This could happen when a landing
// pad is shared by multiple invokes and is also a target of a normal
// edge from elsewhere.
PM.add(createSjLjEHPass(getTargetLowering()));
// FALLTHROUGH
case ExceptionHandling::DwarfCFI:
case ExceptionHandling::ARM:
case ExceptionHandling::Win64:
PM.add(createDwarfEHPass(TM));
break;
case ExceptionHandling::None:
PM.add(createLowerInvokePass(getTargetLowering()));
// The lower invoke pass may create unreachable code. Remove it.
PM.add(createUnreachableBlockEliminationPass());
break;
} }
/// Add common passes that perform LLVM IR to IR transforms in preparation for
/// instruction selection.
void TargetPassConfig::addISelPrepare() {
if (getOptLevel() != CodeGenOpt::None && !DisableCGP) if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
PM.add(createCodeGenPreparePass(getTargetLowering())); PM.add(createCodeGenPreparePass(getTargetLowering()));
@ -202,30 +167,9 @@ bool TargetPassConfig::addCodeGenPasses(MCContext *&OutContext) {
// to ensure that the IR is valid. // to ensure that the IR is valid.
if (!DisableVerify) if (!DisableVerify)
PM.add(createVerifierPass()); PM.add(createVerifierPass());
}
// Standard Lower-Level Passes. void TargetPassConfig::addMachinePasses() {
// Install a MachineModuleInfo class, which is an immutable pass that holds
// all the per-module stuff we're generating, including MCContext.
MachineModuleInfo *MMI =
new MachineModuleInfo(*TM->getMCAsmInfo(), *TM->getRegisterInfo(),
&getTargetLowering()->getObjFileLowering());
PM.add(MMI);
OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
// Set up a MachineFunction for the rest of CodeGen to work on.
PM.add(new MachineFunctionAnalysis(*TM));
// Enable FastISel with -fast, but allow that to be overridden.
if (EnableFastISelOption == cl::BOU_TRUE ||
(getOptLevel() == CodeGenOpt::None &&
EnableFastISelOption != cl::BOU_FALSE))
TM->setFastISel(true);
// Ask the target for an isel.
if (addInstSelector())
return true;
// Print the instruction selected machine code... // Print the instruction selected machine code...
printAndVerify("After Instruction Selection"); printAndVerify("After Instruction Selection");
@ -356,8 +300,6 @@ bool TargetPassConfig::addCodeGenPasses(MCContext *&OutContext) {
if (addPreEmitPass()) if (addPreEmitPass())
printNoVerify("After PreEmit passes"); printNoVerify("After PreEmit passes");
return false;
} }
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//

10
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -111,9 +111,8 @@ namespace {
/// ARM Code Generator Pass Configuration Options. /// ARM Code Generator Pass Configuration Options.
class ARMPassConfig : public TargetPassConfig { class ARMPassConfig : public TargetPassConfig {
public: public:
ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM, ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
bool DisableVerifyFlag) : TargetPassConfig(TM, PM) {}
: TargetPassConfig(TM, PM, DisableVerifyFlag) {}
ARMBaseTargetMachine &getARMTargetMachine() const { ARMBaseTargetMachine &getARMTargetMachine() const {
return getTM<ARMBaseTargetMachine>(); return getTM<ARMBaseTargetMachine>();
@ -131,9 +130,8 @@ public:
}; };
} // namespace } // namespace
TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM, TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
bool DisableVerify) { return new ARMPassConfig(this, PM);
return new ARMPassConfig(this, PM, DisableVerify);
} }
bool ARMPassConfig::addPreISel() { bool ARMPassConfig::addPreISel() {

2
lib/Target/ARM/ARMTargetMachine.h
View File

@ -52,7 +52,7 @@ public:
} }
// Pass Pipeline Configuration // Pass Pipeline Configuration
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, bool DisableVerify); virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE); virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE);
}; };

10
lib/Target/CellSPU/SPUTargetMachine.cpp
View File

@ -55,9 +55,8 @@ namespace {
/// SPU Code Generator Pass Configuration Options. /// SPU Code Generator Pass Configuration Options.
class SPUPassConfig : public TargetPassConfig { class SPUPassConfig : public TargetPassConfig {
public: public:
SPUPassConfig(SPUTargetMachine *TM, PassManagerBase &PM, SPUPassConfig(SPUTargetMachine *TM, PassManagerBase &PM)
bool DisableVerifyFlag) : TargetPassConfig(TM, PM) {}
: TargetPassConfig(TM, PM, DisableVerifyFlag) {}
SPUTargetMachine &getSPUTargetMachine() const { SPUTargetMachine &getSPUTargetMachine() const {
return getTM<SPUTargetMachine>(); return getTM<SPUTargetMachine>();
@ -68,9 +67,8 @@ public:
}; };
} // namespace } // namespace
TargetPassConfig *SPUTargetMachine::createPassConfig(PassManagerBase &PM, TargetPassConfig *SPUTargetMachine::createPassConfig(PassManagerBase &PM) {
bool DisableVerify) { return new SPUPassConfig(this, PM);
return new SPUPassConfig(this, PM, DisableVerify);
} }
bool SPUPassConfig::addInstSelector() { bool SPUPassConfig::addInstSelector() {

3
lib/Target/CellSPU/SPUTargetMachine.h
View File

@ -82,8 +82,7 @@ public:
} }
// Pass Pipeline Configuration // Pass Pipeline Configuration
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
bool DisableVerify);
}; };
} // end namespace llvm } // end namespace llvm

10
lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -80,9 +80,8 @@ namespace {
/// Hexagon Code Generator Pass Configuration Options. /// Hexagon Code Generator Pass Configuration Options.
class HexagonPassConfig : public TargetPassConfig { class HexagonPassConfig : public TargetPassConfig {
public: public:
HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM, HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
bool DisableVerifyFlag) : TargetPassConfig(TM, PM) {}
: TargetPassConfig(TM, PM, DisableVerifyFlag) {}
HexagonTargetMachine &getHexagonTargetMachine() const { HexagonTargetMachine &getHexagonTargetMachine() const {
return getTM<HexagonTargetMachine>(); return getTM<HexagonTargetMachine>();
@ -96,9 +95,8 @@ public:
}; };
} // namespace } // namespace
TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM, TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
bool DisableVerify) { return new HexagonPassConfig(this, PM);
return new HexagonPassConfig(this, PM, DisableVerify);
} }
bool HexagonPassConfig::addInstSelector() { bool HexagonPassConfig::addInstSelector() {

3
lib/Target/Hexagon/HexagonTargetMachine.h
View File

@ -72,8 +72,7 @@ public:
// Pass Pipeline Configuration. // Pass Pipeline Configuration.
virtual bool addPassesForOptimizations(PassManagerBase &PM); virtual bool addPassesForOptimizations(PassManagerBase &PM);
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
bool DisableVerify);
}; };
extern bool flag_aligned_memcpy; extern bool flag_aligned_memcpy;

10
lib/Target/MBlaze/MBlazeTargetMachine.cpp
View File

@ -49,9 +49,8 @@ namespace {
/// MBlaze Code Generator Pass Configuration Options. /// MBlaze Code Generator Pass Configuration Options.
class MBlazePassConfig : public TargetPassConfig { class MBlazePassConfig : public TargetPassConfig {
public: public:
MBlazePassConfig(MBlazeTargetMachine *TM, PassManagerBase &PM, MBlazePassConfig(MBlazeTargetMachine *TM, PassManagerBase &PM)
bool DisableVerifyFlag) : TargetPassConfig(TM, PM) {}
: TargetPassConfig(TM, PM, DisableVerifyFlag) {}
MBlazeTargetMachine &getMBlazeTargetMachine() const { MBlazeTargetMachine &getMBlazeTargetMachine() const {
return getTM<MBlazeTargetMachine>(); return getTM<MBlazeTargetMachine>();
@ -62,9 +61,8 @@ public:
}; };
} // namespace } // namespace
TargetPassConfig *MBlazeTargetMachine::createPassConfig(PassManagerBase &PM, TargetPassConfig *MBlazeTargetMachine::createPassConfig(PassManagerBase &PM) {
bool DisableVerify) { return new MBlazePassConfig(this, PM);
return new MBlazePassConfig(this, PM, DisableVerify);
} }
// Install an instruction selector pass using // Install an instruction selector pass using

3
lib/Target/MBlaze/MBlazeTargetMachine.h
View File

@ -79,8 +79,7 @@ namespace llvm {
} }
// Pass Pipeline Configuration // Pass Pipeline Configuration
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
bool DisableVerify);
}; };
} // End llvm namespace } // End llvm namespace

10
lib/Target/MSP430/MSP430TargetMachine.cpp
View File

@ -42,9 +42,8 @@ namespace {
/// MSP430 Code Generator Pass Configuration Options. /// MSP430 Code Generator Pass Configuration Options.
class MSP430PassConfig : public TargetPassConfig { class MSP430PassConfig : public TargetPassConfig {
public: public:
MSP430PassConfig(MSP430TargetMachine *TM, PassManagerBase &PM, MSP430PassConfig(MSP430TargetMachine *TM, PassManagerBase &PM)
bool DisableVerifyFlag) : TargetPassConfig(TM, PM) {}
: TargetPassConfig(TM, PM, DisableVerifyFlag) {}
MSP430TargetMachine &getMSP430TargetMachine() const { MSP430TargetMachine &getMSP430TargetMachine() const {
return getTM<MSP430TargetMachine>(); return getTM<MSP430TargetMachine>();
@ -55,9 +54,8 @@ public:
}; };
} // namespace } // namespace
TargetPassConfig *MSP430TargetMachine::createPassConfig(PassManagerBase &PM, TargetPassConfig *MSP430TargetMachine::createPassConfig(PassManagerBase &PM) {
bool DisableVerify) { return new MSP430PassConfig(this, PM);
return new MSP430PassConfig(this, PM, DisableVerify);
} }
bool MSP430PassConfig::addInstSelector() { bool MSP430PassConfig::addInstSelector() {

3
lib/Target/MSP430/MSP430TargetMachine.h
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@ -62,8 +62,7 @@ public:
return &TSInfo; return &TSInfo;
} }
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
bool DisableVerify);
}; // MSP430TargetMachine. }; // MSP430TargetMachine.
} // end namespace llvm } // end namespace llvm

10
lib/Target/Mips/MipsTargetMachine.cpp
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@ -93,9 +93,8 @@ namespace {
/// Mips Code Generator Pass Configuration Options. /// Mips Code Generator Pass Configuration Options.
class MipsPassConfig : public TargetPassConfig { class MipsPassConfig : public TargetPassConfig {
public: public:
MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM, MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
bool DisableVerifyFlag) : TargetPassConfig(TM, PM) {}
: TargetPassConfig(TM, PM, DisableVerifyFlag) {}
MipsTargetMachine &getMipsTargetMachine() const { MipsTargetMachine &getMipsTargetMachine() const {
return getTM<MipsTargetMachine>(); return getTM<MipsTargetMachine>();
@ -112,9 +111,8 @@ public:
}; };
} // namespace } // namespace
TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM, TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
bool DisableVerify) { return new MipsPassConfig(this, PM);
return new MipsPassConfig(this, PM, DisableVerify);
} }
// Install an instruction selector pass using // Install an instruction selector pass using

3
lib/Target/Mips/MipsTargetMachine.h
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@ -68,8 +68,7 @@ namespace llvm {
} }
// Pass Pipeline Configuration // Pass Pipeline Configuration
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
bool DisableVerify);
virtual bool addCodeEmitter(PassManagerBase &PM, virtual bool addCodeEmitter(PassManagerBase &PM,
JITCodeEmitter &JCE); JITCodeEmitter &JCE);

17
lib/Target/PTX/PTXTargetMachine.cpp
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@ -109,8 +109,8 @@ namespace {
/// PTX Code Generator Pass Configuration Options. /// PTX Code Generator Pass Configuration Options.
class PTXPassConfig : public TargetPassConfig { class PTXPassConfig : public TargetPassConfig {
public: public:
PTXPassConfig(PTXTargetMachine *TM, PassManagerBase &PM, bool DisableVerifyFlag) PTXPassConfig(PTXTargetMachine *TM, PassManagerBase &PM)
: TargetPassConfig(TM, PM, DisableVerifyFlag) {} : TargetPassConfig(TM, PM) {}
PTXTargetMachine &getPTXTargetMachine() const { PTXTargetMachine &getPTXTargetMachine() const {
return getTM<PTXTargetMachine>(); return getTM<PTXTargetMachine>();
@ -122,9 +122,8 @@ public:
}; };
} // namespace } // namespace
TargetPassConfig *PTXTargetMachine::createPassConfig(PassManagerBase &PM, TargetPassConfig *PTXTargetMachine::createPassConfig(PassManagerBase &PM) {
bool DisableVerify) { return new PTXPassConfig(this, PM);
return new PTXPassConfig(this, PM, DisableVerify);
} }
bool PTXPassConfig::addInstSelector() { bool PTXPassConfig::addInstSelector() {
@ -146,7 +145,13 @@ bool PTXTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
// Add common CodeGen passes. // Add common CodeGen passes.
MCContext *Context = 0; MCContext *Context = 0;
OwningPtr<TargetPassConfig> PassConfig(createPassConfig(PM, DisableVerify));
// FIXME: soon this will be converted to use the exposed TargetPassConfig API.
OwningPtr<PTXPassConfig> PassConfig(
static_cast<PTXPassConfig*>(createPassConfig(PM)));
PassConfig->setDisableVerify(DisableVerify);
if (PassConfig->addCodeGenPasses(Context)) if (PassConfig->addCodeGenPasses(Context))
return true; return true;
assert(Context != 0 && "Failed to get MCContext"); assert(Context != 0 && "Failed to get MCContext");

3
lib/Target/PTX/PTXTargetMachine.h
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@ -81,8 +81,7 @@ class PTXTargetMachine : public LLVMTargetMachine {
} }
// Pass Pipeline Configuration // Pass Pipeline Configuration
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
bool DisableVerify);
}; // class PTXTargetMachine }; // class PTXTargetMachine

10
lib/Target/PowerPC/PPCTargetMachine.cpp
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@ -70,9 +70,8 @@ namespace {
/// PPC Code Generator Pass Configuration Options. /// PPC Code Generator Pass Configuration Options.
class PPCPassConfig : public TargetPassConfig { class PPCPassConfig : public TargetPassConfig {
public: public:
PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM, PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
bool DisableVerifyFlag) : TargetPassConfig(TM, PM) {}
: TargetPassConfig(TM, PM, DisableVerifyFlag) {}
PPCTargetMachine &getPPCTargetMachine() const { PPCTargetMachine &getPPCTargetMachine() const {
return getTM<PPCTargetMachine>(); return getTM<PPCTargetMachine>();
@ -84,9 +83,8 @@ public:
}; };
} // namespace } // namespace
TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM, TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
bool DisableVerify) { return new PPCPassConfig(this, PM);
return new PPCPassConfig(this, PM, DisableVerify);
} }
bool PPCPassConfig::addInstSelector() { bool PPCPassConfig::addInstSelector() {

3
lib/Target/PowerPC/PPCTargetMachine.h
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@ -67,8 +67,7 @@ public:
} }
// Pass Pipeline Configuration // Pass Pipeline Configuration
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
bool DisableVerify);
virtual bool addCodeEmitter(PassManagerBase &PM, virtual bool addCodeEmitter(PassManagerBase &PM,
JITCodeEmitter &JCE); JITCodeEmitter &JCE);
}; };

10
lib/Target/Sparc/SparcTargetMachine.cpp
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@ -42,9 +42,8 @@ namespace {
/// Sparc Code Generator Pass Configuration Options. /// Sparc Code Generator Pass Configuration Options.
class SparcPassConfig : public TargetPassConfig { class SparcPassConfig : public TargetPassConfig {
public: public:
SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM, SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
bool DisableVerifyFlag) : TargetPassConfig(TM, PM) {}
: TargetPassConfig(TM, PM, DisableVerifyFlag) {}
SparcTargetMachine &getSparcTargetMachine() const { SparcTargetMachine &getSparcTargetMachine() const {
return getTM<SparcTargetMachine>(); return getTM<SparcTargetMachine>();
@ -55,9 +54,8 @@ public:
}; };
} // namespace } // namespace
TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM, TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
bool DisableVerify) { return new SparcPassConfig(this, PM);
return new SparcPassConfig(this, PM, DisableVerify);
} }
bool SparcPassConfig::addInstSelector() { bool SparcPassConfig::addInstSelector() {

3
lib/Target/Sparc/SparcTargetMachine.h
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@ -55,8 +55,7 @@ public:
virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const TargetData *getTargetData() const { return &DataLayout; }
// Pass Pipeline Configuration // Pass Pipeline Configuration
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
bool DisableVerify);
}; };
/// SparcV8TargetMachine - Sparc 32-bit target machine /// SparcV8TargetMachine - Sparc 32-bit target machine

10
lib/Target/X86/X86TargetMachine.cpp
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@ -121,9 +121,8 @@ namespace {
/// X86 Code Generator Pass Configuration Options. /// X86 Code Generator Pass Configuration Options.
class X86PassConfig : public TargetPassConfig { class X86PassConfig : public TargetPassConfig {
public: public:
X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM, X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
bool DisableVerifyFlag) : TargetPassConfig(TM, PM) {}
: TargetPassConfig(TM, PM, DisableVerifyFlag) {}
X86TargetMachine &getX86TargetMachine() const { X86TargetMachine &getX86TargetMachine() const {
return getTM<X86TargetMachine>(); return getTM<X86TargetMachine>();
@ -140,9 +139,8 @@ public:
}; };
} // namespace } // namespace
TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM, TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
bool DisableVerify) { return new X86PassConfig(this, PM);
return new X86PassConfig(this, PM, DisableVerify);
} }
bool X86PassConfig::addInstSelector() { bool X86PassConfig::addInstSelector() {

3
lib/Target/X86/X86TargetMachine.h
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@ -71,8 +71,7 @@ public:
} }
// Set up the pass pipeline. // Set up the pass pipeline.
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
bool DisableVerify);
virtual bool addCodeEmitter(PassManagerBase &PM, virtual bool addCodeEmitter(PassManagerBase &PM,
JITCodeEmitter &JCE); JITCodeEmitter &JCE);

10
lib/Target/XCore/XCoreTargetMachine.cpp
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@ -39,9 +39,8 @@ namespace {
/// XCore Code Generator Pass Configuration Options. /// XCore Code Generator Pass Configuration Options.
class XCorePassConfig : public TargetPassConfig { class XCorePassConfig : public TargetPassConfig {
public: public:
XCorePassConfig(XCoreTargetMachine *TM, PassManagerBase &PM, XCorePassConfig(XCoreTargetMachine *TM, PassManagerBase &PM)
bool DisableVerifyFlag) : TargetPassConfig(TM, PM) {}
: TargetPassConfig(TM, PM, DisableVerifyFlag) {}
XCoreTargetMachine &getXCoreTargetMachine() const { XCoreTargetMachine &getXCoreTargetMachine() const {
return getTM<XCoreTargetMachine>(); return getTM<XCoreTargetMachine>();
@ -51,9 +50,8 @@ public:
}; };
} // namespace } // namespace
TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM, TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) {
bool DisableVerify) { return new XCorePassConfig(this, PM);
return new XCorePassConfig(this, PM, DisableVerify);
} }
bool XCorePassConfig::addInstSelector() { bool XCorePassConfig::addInstSelector() {

3
lib/Target/XCore/XCoreTargetMachine.h
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@ -56,8 +56,7 @@ public:
virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const TargetData *getTargetData() const { return &DataLayout; }
// Pass Pipeline Configuration // Pass Pipeline Configuration
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
bool DisableVerify);
}; };
} // end namespace llvm } // end namespace llvm