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Add support for the arm 'y' asm modifier.
Fixes part of rdar://9444657 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132011 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -404,6 +404,18 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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case 'q': // Print a NEON quad precision register.
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printOperand(MI, OpNum, O);
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return false;
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case 'y': // Print a VFP single precision register as indexed double.
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// This uses the ordering of the alias table to get the first 'd' register
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// that overlaps the 's' register. Also, s0 is an odd register, hence the
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// odd modulus check below.
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if (MI->getOperand(OpNum).isReg()) {
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unsigned Reg = MI->getOperand(OpNum).getReg();
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const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
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O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
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(((Reg % 2) == 1) ? "[0]" : "[1]");
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return false;
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}
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// Fallthrough to unsupported.
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case 'Q':
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case 'R':
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case 'H':
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15
test/CodeGen/ARM/arm-modifier.ll
Normal file
15
test/CodeGen/ARM/arm-modifier.ll
Normal file
@ -0,0 +1,15 @@
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; RUN: llc < %s -march=arm -mattr=+vfp2
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define i32 @foo(float %scale, float %scale2) nounwind ssp {
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entry:
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%scale.addr = alloca float, align 4
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%scale2.addr = alloca float, align 4
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store float %scale, float* %scale.addr, align 4
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store float %scale2, float* %scale2.addr, align 4
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%tmp = load float* %scale.addr, align 4
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%tmp1 = load float* %scale2.addr, align 4
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call void asm sideeffect "vmul.f32 q0, q0, ${0:y} \0A\09vmul.f32 q1, q1, ${0:y} \0A\09vmul.f32 q1, q0, ${1:y} \0A\09", "w,w,~{q0},~{q1}"(float %tmp, float %tmp1) nounwind, !srcloc !0
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ret i32 0
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}
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!0 = metadata !{i32 56, i32 89, i32 128, i32 168}
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