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Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, just like it now knows for FMULs.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156029 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2012-05-02 22:17:40 +00:00
parent c0f0a93936
commit 062c0a5b58
2 changed files with 27 additions and 0 deletions
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18
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -215,6 +215,7 @@ namespace {
SDValue visitFADD(SDNode *N); SDValue visitFADD(SDNode *N);
SDValue visitFSUB(SDNode *N); SDValue visitFSUB(SDNode *N);
SDValue visitFMUL(SDNode *N); SDValue visitFMUL(SDNode *N);
SDValue visitFMA(SDNode *N);
SDValue visitFDIV(SDNode *N); SDValue visitFDIV(SDNode *N);
SDValue visitFREM(SDNode *N); SDValue visitFREM(SDNode *N);
SDValue visitFCOPYSIGN(SDNode *N); SDValue visitFCOPYSIGN(SDNode *N);
@ -1126,6 +1127,7 @@ SDValue DAGCombiner::visit(SDNode *N) {
case ISD::FADD: return visitFADD(N); case ISD::FADD: return visitFADD(N);
case ISD::FSUB: return visitFSUB(N); case ISD::FSUB: return visitFSUB(N);
case ISD::FMUL: return visitFMUL(N); case ISD::FMUL: return visitFMUL(N);
case ISD::FMA: return visitFMA(N);
case ISD::FDIV: return visitFDIV(N); case ISD::FDIV: return visitFDIV(N);
case ISD::FREM: return visitFREM(N); case ISD::FREM: return visitFREM(N);
case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
@ -5751,6 +5753,22 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) {
return SDValue(); return SDValue();
} }
SDValue DAGCombiner::visitFMA(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
EVT VT = N->getValueType(0);
if (N0CFP && N0CFP->isExactlyValue(1.0))
return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2);
if (N1CFP && N1CFP->isExactlyValue(1.0))
return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2);
return SDValue();
}
SDValue DAGCombiner::visitFDIV(SDNode *N) { SDValue DAGCombiner::visitFDIV(SDNode *N) {
SDValue N0 = N->getOperand(0); SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1); SDValue N1 = N->getOperand(1);

9
test/CodeGen/ARM/fusedMAC.ll
View File

@ -180,6 +180,15 @@ entry:
ret double %tmp3 ret double %tmp3
} }
define float @test_fma_const_fold(float %a, float %b) nounwind {
; CHECK: test_fma_const_fold
; CHECK-NOT: vfma
; CHECK-NOT: vmul
; CHECK: vadd
%ret = call float @llvm.fma.f32(float %a, float 1.0, float %b)
ret float %ret
}
declare float @llvm.fma.f32(float, float, float) nounwind readnone declare float @llvm.fma.f32(float, float, float) nounwind readnone
declare double @llvm.fma.f64(double, double, double) nounwind readnone declare double @llvm.fma.f64(double, double, double) nounwind readnone
declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone