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Update this pass to set PhysRegsUsed info in MachineFunction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19792 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-01-23 22:51:56 +00:00
parent b0f31bf19b
commit 0648b16c48
1 changed files with 13 additions and 1 deletions
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14
lib/CodeGen/RegAllocLocal.cpp
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@ -38,6 +38,7 @@ namespace {
MachineFunction *MF; MachineFunction *MF;
const MRegisterInfo *RegInfo; const MRegisterInfo *RegInfo;
LiveVariables *LV; LiveVariables *LV;
bool *PhysRegsEverUsed;
// StackSlotForVirtReg - Maps virtual regs to the frame index where these // StackSlotForVirtReg - Maps virtual regs to the frame index where these
// values are spilled. // values are spilled.
@ -478,6 +479,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex); RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex);
++NumLoads; // Update statistics ++NumLoads; // Update statistics
PhysRegsEverUsed[PhysReg] = true;
MI->SetMachineOperandReg(OpNum, PhysReg); // Assign the input register MI->SetMachineOperandReg(OpNum, PhysReg); // Assign the input register
return MI; return MI;
} }
@ -547,6 +549,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
if (MO.isDef() && MO.isRegister() && MO.getReg() && if (MO.isDef() && MO.isRegister() && MO.getReg() &&
MRegisterInfo::isPhysicalRegister(MO.getReg())) { MRegisterInfo::isPhysicalRegister(MO.getReg())) {
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
PhysRegsEverUsed[Reg] = true;
spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the reg spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the reg
PhysRegsUsed[Reg] = 0; // It is free and reserved now PhysRegsUsed[Reg] = 0; // It is free and reserved now
PhysRegsUseOrder.push_back(Reg); PhysRegsUseOrder.push_back(Reg);
@ -554,6 +557,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
*AliasSet; ++AliasSet) { *AliasSet; ++AliasSet) {
PhysRegsUseOrder.push_back(*AliasSet); PhysRegsUseOrder.push_back(*AliasSet);
PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
PhysRegsEverUsed[*AliasSet] = true;
} }
} }
} }
@ -565,16 +569,19 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
spillPhysReg(MBB, MI, Reg, true); spillPhysReg(MBB, MI, Reg, true);
PhysRegsUseOrder.push_back(Reg); PhysRegsUseOrder.push_back(Reg);
PhysRegsUsed[Reg] = 0; // It is free and reserved now PhysRegsUsed[Reg] = 0; // It is free and reserved now
PhysRegsEverUsed[Reg] = true;
for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
*AliasSet; ++AliasSet) { *AliasSet; ++AliasSet) {
PhysRegsUseOrder.push_back(*AliasSet); PhysRegsUseOrder.push_back(*AliasSet);
PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
PhysRegsEverUsed[*AliasSet] = true;
} }
} }
// Okay, we have allocated all of the source operands and spilled any values // Okay, we have allocated all of the source operands and spilled any values
// that would be destroyed by defs of this instruction. Loop over the // that would be destroyed by defs of this instruction. Loop over the
// implicit defs and assign them to a register, spilling incoming values if // explicit defs and assign them to a register, spilling incoming values if
// we need to scavenge a register. // we need to scavenge a register.
// //
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
@ -587,6 +594,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
// If DestVirtReg already has a value, use it. // If DestVirtReg already has a value, use it.
if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
DestPhysReg = getReg(MBB, MI, DestVirtReg); DestPhysReg = getReg(MBB, MI, DestVirtReg);
PhysRegsEverUsed[DestPhysReg] = true;
markVirtRegModified(DestVirtReg); markVirtRegModified(DestVirtReg);
MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register
} }
@ -652,6 +660,10 @@ bool RA::runOnMachineFunction(MachineFunction &Fn) {
RegInfo = TM->getRegisterInfo(); RegInfo = TM->getRegisterInfo();
LV = &getAnalysis<LiveVariables>(); LV = &getAnalysis<LiveVariables>();
PhysRegsEverUsed = new bool[RegInfo->getNumRegs()];
std::fill(PhysRegsEverUsed, PhysRegsEverUsed+RegInfo->getNumRegs(), false);
Fn.setUsedPhysRegs(PhysRegsEverUsed);
PhysRegsUsed.assign(RegInfo->getNumRegs(), -1); PhysRegsUsed.assign(RegInfo->getNumRegs(), -1);
// initialize the virtual->physical register map to have a 'null' // initialize the virtual->physical register map to have a 'null'