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[mips][mips64r6] Add addiupc, aluipc, and auipc
Summary: No support for symbols in place of the immediate yet since it requires new relocations. Depends on D3671 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3689 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208858 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -263,6 +263,9 @@ static DecodeStatus DecodeExtSize(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
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/// handle.
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template <typename InsnType>
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@ -908,3 +911,9 @@ static DecodeStatus DecodeExtSize(MCInst &Inst,
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Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2));
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return MCDisassembler::Success;
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}
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@ -548,5 +548,15 @@ MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
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return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1;
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}
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#include "MipsGenMCCodeEmitter.inc"
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unsigned
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MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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assert(MI.getOperand(OpNo).isImm());
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// The immediate is encoded as 'immediate << 2'.
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unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
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assert((Res & 3) == 0);
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return Res >> 2;
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}
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#include "MipsGenMCCodeEmitter.inc"
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@ -116,6 +116,10 @@ public:
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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@ -26,12 +26,20 @@ class MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
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def OPGROUP_COP1 { bits<6> Value = 0b010001; }
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def OPGROUP_AUI { bits<6> Value = 0b001111; }
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def OPGROUP_DAUI { bits<6> Value = 0b011101; }
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def OPGROUP_PCREL { bits<6> Value = 0b111011; }
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def OPGROUP_REGIMM { bits<6> Value = 0b000001; }
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def OPGROUP_SPECIAL { bits<6> Value = 0b000000; }
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class OPCODE2<bits<2> Val> {
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bits<2> Value = Val;
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}
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def OPCODE2_ADDIUPC : OPCODE2<0b00>;
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class OPCODE5<bits<5> Val> {
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bits<5> Value = Val;
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}
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def OPCODE5_ALUIPC : OPCODE5<0b11111>;
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def OPCODE5_AUIPC : OPCODE5<0b11110>;
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def OPCODE5_DAHI : OPCODE5<0b00110>;
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def OPCODE5_DATI : OPCODE5<0b11110>;
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@ -79,6 +87,30 @@ class COP1_3R_FM<bits<6> funct, FIELD_FMT Format> : MipsR6Inst {
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let Inst{5-0} = funct;
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}
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class PCREL16_FM<OPCODE5 Operation> : MipsR6Inst {
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bits<5> rs;
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bits<16> imm;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_PCREL.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = Operation.Value;
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let Inst{15-0} = imm;
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}
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class PCREL19_FM<OPCODE2 Operation> : MipsR6Inst {
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bits<5> rs;
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bits<19> imm;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_PCREL.Value;
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let Inst{25-21} = rs;
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let Inst{20-19} = Operation.Value;
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let Inst{18-0} = imm;
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}
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class SPECIAL_3R_FM<bits<5> mulop, bits<6> funct> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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@ -58,7 +58,10 @@ include "Mips32r6InstrFormats.td"
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//
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//===----------------------------------------------------------------------===//
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class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
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class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
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class AUI_ENC : AUI_FM;
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class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
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class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
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class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
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class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
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@ -76,6 +79,25 @@ class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
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//
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//===----------------------------------------------------------------------===//
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class ADDIUPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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dag OutOperandList = (outs GPROpnd:$rs);
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dag InOperandList = (ins simm19_lsl2:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
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list<dag> Pattern = [];
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}
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class ADDIUPC_DESC : ADDIUPC_DESC_BASE<"addiupc", GPR32Opnd>;
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class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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dag OutOperandList = (outs GPROpnd:$rs);
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dag InOperandList = (ins simm16:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
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list<dag> Pattern = [];
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}
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class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
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class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
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class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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dag OutOperandList = (outs GPROpnd:$rs);
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dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
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@ -126,11 +148,11 @@ class SEL_S_DESC : SEL_DESC_BASE<"sel.s", FGR32Opnd>;
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//
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//===----------------------------------------------------------------------===//
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def ADDIUPC;
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def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
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def ALIGN; // Known as as BALIGN in DSP ASE
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def ALUIPC;
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def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
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def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
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def AUIPC;
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def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
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def BALC;
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def BC1EQZ;
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def BC1NEZ;
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@ -117,6 +117,7 @@ private:
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unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getLSAImmEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getSimm19Lsl2Encoding(const MachineInstr &MI, unsigned OpNo) const;
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/// Expand pseudo instructions with accumulator register operands.
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void expandACCInstr(MachineBasicBlock::instr_iterator MI,
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@ -248,6 +249,12 @@ unsigned MipsCodeEmitter::getLSAImmEncoding(const MachineInstr &MI,
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return 0;
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}
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unsigned MipsCodeEmitter::getSimm19Lsl2Encoding(const MachineInstr &MI,
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unsigned OpNo) const {
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llvm_unreachable("Unimplemented function.");
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return 0;
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}
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned MipsCodeEmitter::getMachineOpValue(const MachineInstr &MI,
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@ -316,6 +316,11 @@ def simm16 : Operand<i32> {
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let DecoderMethod= "DecodeSimm16";
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}
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def simm19_lsl2 : Operand<i32> {
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let EncoderMethod = "getSimm19Lsl2Encoding";
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let DecoderMethod = "DecodeSimm19Lsl2";
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}
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def simm20 : Operand<i32> {
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}
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@ -4,7 +4,10 @@
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.set noat
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# FIXME: Add the instructions carried forward from older ISA's
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addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0xec,0x80,0x00,0x19]
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aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38]
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aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9]
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auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff]
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div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a]
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divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b]
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mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda]
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@ -4,7 +4,10 @@
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.set noat
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# FIXME: Add the instructions carried forward from older ISA's
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addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0xec,0x80,0x00,0x19]
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aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38]
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aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9]
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auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff]
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daui $3,$2,0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x62,0x12,0x34]
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dahi $3,$3,0x5678 # CHECK: dahi $3, $3, 22136 # encoding: [0x04,0x66,0x56,0x78]
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dati $3,$3,0xabcd # CHECK: dati $3, $3, 43981 # encoding: [0x04,0x7e,0xab,0xcd]
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