From 069bcd7b38ef4bbc323cc3e0d64bc4bea24be924 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Mon, 14 Apr 2014 13:18:40 +0000 Subject: [PATCH] AArch64: add newline to end of test files. Should be no other change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206174 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/AArch64/neon-add-pairwise.ll | 2 +- test/CodeGen/AArch64/neon-add-sub.ll | 2 +- test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll | 2 +- test/CodeGen/AArch64/neon-diagnostics.ll | 2 +- test/CodeGen/AArch64/neon-max-min-pairwise.ll | 2 +- test/CodeGen/AArch64/neon-misc.ll | 2 +- test/CodeGen/AArch64/neon-scalar-neg.ll | 2 +- test/CodeGen/AArch64/neon-simd-shift.ll | 2 +- test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll | 2 +- test/CodeGen/AArch64/neon-truncStore-extLoad.ll | 2 +- test/CodeGen/AArch64/neon-vector-list-spill.ll | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/test/CodeGen/AArch64/neon-add-pairwise.ll b/test/CodeGen/AArch64/neon-add-pairwise.ll index 32d8222ded2..26f91477485 100644 --- a/test/CodeGen/AArch64/neon-add-pairwise.ll +++ b/test/CodeGen/AArch64/neon-add-pairwise.ll @@ -98,4 +98,4 @@ define i32 @test_vaddv.v2i32(<2 x i32> %a) { ret i32 %2 } -declare <1 x i32> @llvm.aarch64.neon.vaddv.v1i32.v2i32(<2 x i32>) \ No newline at end of file +declare <1 x i32> @llvm.aarch64.neon.vaddv.v1i32.v2i32(<2 x i32>) diff --git a/test/CodeGen/AArch64/neon-add-sub.ll b/test/CodeGen/AArch64/neon-add-sub.ll index 9015237fddc..25d2dcb7ceb 100644 --- a/test/CodeGen/AArch64/neon-add-sub.ll +++ b/test/CodeGen/AArch64/neon-add-sub.ll @@ -276,4 +276,4 @@ define <1 x i32> @test_sub_v1i32(<1 x i32> %a, <1 x i32> %b) { ;CHECK: sub {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s %c = sub <1 x i32> %a, %b ret <1 x i32> %c -} \ No newline at end of file +} diff --git a/test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll b/test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll index 4dffcd169e7..8b9fde3f851 100644 --- a/test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll +++ b/test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll @@ -44,4 +44,4 @@ entry: declare { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2lane.v4i32(i8*, <4 x i32>, <4 x i32>, i32, i32) declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) -declare { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) \ No newline at end of file +declare { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) diff --git a/test/CodeGen/AArch64/neon-diagnostics.ll b/test/CodeGen/AArch64/neon-diagnostics.ll index f546aa7d334..099b6856cec 100644 --- a/test/CodeGen/AArch64/neon-diagnostics.ll +++ b/test/CodeGen/AArch64/neon-diagnostics.ll @@ -21,4 +21,4 @@ define <4 x i32> @test_vshrn_not_match(<2 x i32> %a, <2 x i64> %b) { %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %3, <2 x i32> %4 = bitcast <2 x i64> %shuffle.i to <4 x i32> ret <4 x i32> %4 -} \ No newline at end of file +} diff --git a/test/CodeGen/AArch64/neon-max-min-pairwise.ll b/test/CodeGen/AArch64/neon-max-min-pairwise.ll index 3e18077337d..12d66a4c110 100644 --- a/test/CodeGen/AArch64/neon-max-min-pairwise.ll +++ b/test/CodeGen/AArch64/neon-max-min-pairwise.ll @@ -343,4 +343,4 @@ define i32 @test_vmaxv_u32(<2 x i32> %a) { declare <1 x i32> @llvm.aarch64.neon.uminv.v1i32.v2i32(<2 x i32>) declare <1 x i32> @llvm.aarch64.neon.sminv.v1i32.v2i32(<2 x i32>) declare <1 x i32> @llvm.aarch64.neon.umaxv.v1i32.v2i32(<2 x i32>) -declare <1 x i32> @llvm.aarch64.neon.smaxv.v1i32.v2i32(<2 x i32>) \ No newline at end of file +declare <1 x i32> @llvm.aarch64.neon.smaxv.v1i32.v2i32(<2 x i32>) diff --git a/test/CodeGen/AArch64/neon-misc.ll b/test/CodeGen/AArch64/neon-misc.ll index 7ec36c213d4..6e9bfbbc71c 100644 --- a/test/CodeGen/AArch64/neon-misc.ll +++ b/test/CodeGen/AArch64/neon-misc.ll @@ -2011,4 +2011,4 @@ define i64 @test_vaddlv_u32(<2 x i32> %a) { } declare <1 x i64> @llvm.aarch64.neon.saddlv.v1i64.v2i32(<2 x i32>) -declare <1 x i64> @llvm.aarch64.neon.uaddlv.v1i64.v2i32(<2 x i32>) \ No newline at end of file +declare <1 x i64> @llvm.aarch64.neon.uaddlv.v1i64.v2i32(<2 x i32>) diff --git a/test/CodeGen/AArch64/neon-scalar-neg.ll b/test/CodeGen/AArch64/neon-scalar-neg.ll index 4dc9d519783..b48e86887af 100644 --- a/test/CodeGen/AArch64/neon-scalar-neg.ll +++ b/test/CodeGen/AArch64/neon-scalar-neg.ll @@ -58,4 +58,4 @@ entry: ret i64 %0 } -declare <1 x i64> @llvm.arm.neon.vqneg.v1i64(<1 x i64>) \ No newline at end of file +declare <1 x i64> @llvm.arm.neon.vqneg.v1i64(<1 x i64>) diff --git a/test/CodeGen/AArch64/neon-simd-shift.ll b/test/CodeGen/AArch64/neon-simd-shift.ll index fd762656e56..b87d72e48ed 100644 --- a/test/CodeGen/AArch64/neon-simd-shift.ll +++ b/test/CodeGen/AArch64/neon-simd-shift.ll @@ -1553,4 +1553,4 @@ define <1 x double> @test_vcvt_n_f64_u64(<1 x i64> %a) { declare <1 x i64> @llvm.arm.neon.vcvtfp2fxs.v1i64.v1f64(<1 x double>, i32) declare <1 x i64> @llvm.arm.neon.vcvtfp2fxu.v1i64.v1f64(<1 x double>, i32) declare <1 x double> @llvm.arm.neon.vcvtfxs2fp.v1f64.v1i64(<1 x i64>, i32) -declare <1 x double> @llvm.arm.neon.vcvtfxu2fp.v1f64.v1i64(<1 x i64>, i32) \ No newline at end of file +declare <1 x double> @llvm.arm.neon.vcvtfxu2fp.v1f64.v1i64(<1 x i64>, i32) diff --git a/test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll b/test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll index bb3300ee9a9..b9396ac2e47 100644 --- a/test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll +++ b/test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll @@ -27,4 +27,4 @@ define void @spill_fpr16(%bigtype_v1i16* %addr) { store volatile %bigtype_v1i16 %val1, %bigtype_v1i16* %addr store volatile %bigtype_v1i16 %val2, %bigtype_v1i16* %addr ret void -} \ No newline at end of file +} diff --git a/test/CodeGen/AArch64/neon-truncStore-extLoad.ll b/test/CodeGen/AArch64/neon-truncStore-extLoad.ll index e5b76942446..96435e176c7 100644 --- a/test/CodeGen/AArch64/neon-truncStore-extLoad.ll +++ b/test/CodeGen/AArch64/neon-truncStore-extLoad.ll @@ -54,4 +54,4 @@ define i32 @loadExt.i32(<4 x i8>* %ref) { %vecext = extractelement <4 x i8> %a, i32 0 %conv = zext i8 %vecext to i32 ret i32 %conv -} \ No newline at end of file +} diff --git a/test/CodeGen/AArch64/neon-vector-list-spill.ll b/test/CodeGen/AArch64/neon-vector-list-spill.ll index 3ab69c4a02a..a04937e72ac 100644 --- a/test/CodeGen/AArch64/neon-vector-list-spill.ll +++ b/test/CodeGen/AArch64/neon-vector-list-spill.ll @@ -172,4 +172,4 @@ define <8 x i16> @test_4xFPR128Lo(i64 %got, i8* %ptr, <1 x i64> %a) { declare void @llvm.arm.neon.vst2lane.v1i64(i8*, <1 x i64>, <1 x i64>, i32, i32) declare void @llvm.arm.neon.vst3lane.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, i32, i32) -declare void @llvm.arm.neon.vst4lane.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32, i32) \ No newline at end of file +declare void @llvm.arm.neon.vst4lane.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32, i32)