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Don't fold insufficiently aligned ldr/str into ldm/stm instructions.

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An unaligned ldr causes a trap, and is then emulated by the kernel with
awesome performance. The darwin kernel does not emulate unaligned ldm/stm
Thumb2 instructions, so don't generate them.

This fixes the miscompilation of Multisource/Applications/JM/lencod for Thumb2.

Generating unaligned ldr/str pairs from a 16-bit aligned memcpy is probably
also a bad idea, but that is beyond the scope of this patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93393 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2010-01-14 00:54:10 +00:00
parent b7eaa130d0
commit 069e100f9a
1 changed files with 12 additions and 0 deletions
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12
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@ -740,6 +740,18 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
/// isMemoryOp - Returns true if instruction is a memory operations (that this /// isMemoryOp - Returns true if instruction is a memory operations (that this
/// pass is capable of operating on). /// pass is capable of operating on).
static bool isMemoryOp(const MachineInstr *MI) { static bool isMemoryOp(const MachineInstr *MI) {
if (MI->hasOneMemOperand()) {
const MachineMemOperand *MMO = *MI->memoperands_begin();
// Don't touch volatile memory accesses - we may be changing their order.
if (MMO->isVolatile())
return false;
// Unaligned ldr/str is emulated by some kernels, but unaligned ldm/stm is not.
if (MMO->getAlignment() < 4)
return false;
}
int Opcode = MI->getOpcode(); int Opcode = MI->getOpcode();
switch (Opcode) { switch (Opcode) {
default: break; default: break;