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VDUP doesn't support vectors with 64-bit elements.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104455 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
2010-05-23 05:42:31 +00:00
parent 62e4c671b6
commit 069e434868
1 changed files with 2 additions and 2 deletions
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4
lib/Target/ARM/ARMISelLowering.cpp
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@@ -2876,12 +2876,12 @@ static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
return SDValue(); return SDValue();
// Use VDUP for non-constant splats. // Use VDUP for non-constant splats.
if (usesOnlyOneValue) unsigned EltSize = VT.getVectorElementType().getSizeInBits();
if (usesOnlyOneValue && EltSize <= 32)
return DAG.getNode(ARMISD::VDUP, dl, VT, Value); return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
// Vectors with 32- or 64-bit elements can be built by directly assigning // Vectors with 32- or 64-bit elements can be built by directly assigning
// the subregisters. // the subregisters.
unsigned EltSize = VT.getVectorElementType().getSizeInBits();
if (EltSize >= 32) { if (EltSize >= 32) {
// Do the expansion with floating-point types, since that is what the VFP // Do the expansion with floating-point types, since that is what the VFP
// registers are defined to use, and since i64 is not legal. // registers are defined to use, and since i64 is not legal.