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Shrink shifts when possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28136 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1615,6 +1615,18 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) {
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DAG.getConstant(c1 + c2, N1.getValueType()));
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DAG.getConstant(c1 + c2, N1.getValueType()));
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}
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}
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// fold (srl (anyextend x), c) -> (anyextend (srl x, c))
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if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
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// Shifting in all undef bits?
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MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
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if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
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return DAG.getNode(ISD::UNDEF, VT);
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SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
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AddToWorkList(SmallShift.Val);
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return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
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}
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// fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
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// fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
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if (N1C && N0.getOpcode() == ISD::CTLZ &&
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if (N1C && N0.getOpcode() == ISD::CTLZ &&
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N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
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N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
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