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Shrink shifts when possible.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28136 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-05-05 22:53:17 +00:00
parent fe8babf689
commit 06afe07037
1 changed files with 12 additions and 0 deletions
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12
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -1615,6 +1615,18 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) {
DAG.getConstant(c1 + c2, N1.getValueType())); DAG.getConstant(c1 + c2, N1.getValueType()));
} }
// fold (srl (anyextend x), c) -> (anyextend (srl x, c))
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
// Shifting in all undef bits?
MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
return DAG.getNode(ISD::UNDEF, VT);
SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
AddToWorkList(SmallShift.Val);
return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
}
// fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
if (N1C && N0.getOpcode() == ISD::CTLZ && if (N1C && N0.getOpcode() == ISD::CTLZ &&
N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {