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Do not emit intermediate register for zero FP immediate

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This updates check for double precision zero floating point constant to allow
use of instruction with immediate value rather than temporary register.
Currently "a == 0.0", where "a" is of "double" type generates:

vmov.i32        d16, #0x0
vcmpe.f64       d0, d16

With this change it becomes:

vcmpe.f64        d0, #0

Patch by Sergey Dmitrouk.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220486 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Renato Golin 2014-10-23 15:31:50 +00:00
parent 8b8e2b2f81
commit 06b11e36e5
2 changed files with 24 additions and 0 deletions
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12
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -3245,6 +3245,18 @@ static bool isFloatingPointZero(SDValue Op) {
if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
return CFP->getValueAPF().isPosZero();
}
} else if (Op->getOpcode() == ISD::BITCAST &&
Op->getValueType(0) == MVT::f64) {
// Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
// created by LowerConstantFP().
SDValue BitcastOp = Op->getOperand(0);
if (BitcastOp->getOpcode() == ARMISD::VMOVIMM) {
SDValue MoveOp = BitcastOp->getOperand(0);
if (MoveOp->getOpcode() == ISD::TargetConstant &&
cast<ConstantSDNode>(MoveOp)->getZExtValue() == 0) {
return true;
}
}
}
return false;
}

12
test/CodeGen/ARM/fpcmp-f64-neon-opt.ll Normal file
View File

@ -0,0 +1,12 @@
; RUN: llc -mtriple=linux-arm-gnueabihf -mattr=+neon %s -o - | FileCheck %s
; Check that no intermediate integer register is used.
define i32 @no-intermediate-register-for-zero-imm(double %x) #0 {
entry:
; CHECK-LABEL: no-intermediate-register-for-zero-imm
; CHECK-NOT: vmov
; CHECK: vcmp
%cmp = fcmp une double %x, 0.000000e+00
%conv = zext i1 %cmp to i32
ret i32 %conv
}