mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-06 14:57:41 +00:00
Follow up on r127913. Fix Thumb revsh isel. rdar://9286766
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129548 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
3ec01b7dac
commit
06b2a60ef9
@ -1184,10 +1184,18 @@ def tREVSH : // A8.6.136
|
|||||||
"revsh", "\t$Rd, $Rm",
|
"revsh", "\t$Rd, $Rm",
|
||||||
[(set tGPR:$Rd,
|
[(set tGPR:$Rd,
|
||||||
(sext_inreg
|
(sext_inreg
|
||||||
(or (srl (and tGPR:$Rm, 0xFF00), (i32 8)),
|
(or (srl tGPR:$Rm, (i32 8)),
|
||||||
(shl tGPR:$Rm, (i32 8))), i16))]>,
|
(shl tGPR:$Rm, (i32 8))), i16))]>,
|
||||||
Requires<[IsThumb, IsThumb1Only, HasV6]>;
|
Requires<[IsThumb, IsThumb1Only, HasV6]>;
|
||||||
|
|
||||||
|
def : T1Pat<(sext_inreg (or (srl (and tGPR:$Rm, 0xFF00), (i32 8)),
|
||||||
|
(shl tGPR:$Rm, (i32 8))), i16),
|
||||||
|
(tREVSH tGPR:$Rm)>,
|
||||||
|
Requires<[IsThumb, IsThumb1Only, HasV6]>;
|
||||||
|
|
||||||
|
def : T1Pat<(sra (bswap tGPR:$Rm), (i32 16)), (tREVSH tGPR:$Rm)>,
|
||||||
|
Requires<[IsThumb, IsThumb1Only, HasV6]>;
|
||||||
|
|
||||||
// Rotate right register
|
// Rotate right register
|
||||||
def tROR : // A8.6.139
|
def tROR : // A8.6.139
|
||||||
T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
|
T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
|
||||||
|
56
test/CodeGen/Thumb/rev.ll
Normal file
56
test/CodeGen/Thumb/rev.ll
Normal file
@ -0,0 +1,56 @@
|
|||||||
|
; RUN: llc < %s -march=thumb -mattr=+v6 | FileCheck %s
|
||||||
|
|
||||||
|
define i32 @test1(i32 %X) nounwind {
|
||||||
|
; CHECK: test1
|
||||||
|
; CHECK: rev16 r0, r0
|
||||||
|
%tmp1 = lshr i32 %X, 8
|
||||||
|
%X15 = bitcast i32 %X to i32
|
||||||
|
%tmp4 = shl i32 %X15, 8
|
||||||
|
%tmp2 = and i32 %tmp1, 16711680
|
||||||
|
%tmp5 = and i32 %tmp4, -16777216
|
||||||
|
%tmp9 = and i32 %tmp1, 255
|
||||||
|
%tmp13 = and i32 %tmp4, 65280
|
||||||
|
%tmp6 = or i32 %tmp5, %tmp2
|
||||||
|
%tmp10 = or i32 %tmp6, %tmp13
|
||||||
|
%tmp14 = or i32 %tmp10, %tmp9
|
||||||
|
ret i32 %tmp14
|
||||||
|
}
|
||||||
|
|
||||||
|
define i32 @test2(i32 %X) nounwind {
|
||||||
|
; CHECK: test2
|
||||||
|
; CHECK: revsh r0, r0
|
||||||
|
%tmp1 = lshr i32 %X, 8
|
||||||
|
%tmp1.upgrd.1 = trunc i32 %tmp1 to i16
|
||||||
|
%tmp3 = trunc i32 %X to i16
|
||||||
|
%tmp2 = and i16 %tmp1.upgrd.1, 255
|
||||||
|
%tmp4 = shl i16 %tmp3, 8
|
||||||
|
%tmp5 = or i16 %tmp2, %tmp4
|
||||||
|
%tmp5.upgrd.2 = sext i16 %tmp5 to i32
|
||||||
|
ret i32 %tmp5.upgrd.2
|
||||||
|
}
|
||||||
|
|
||||||
|
; rdar://9147637
|
||||||
|
define i32 @test3(i16 zeroext %a) nounwind {
|
||||||
|
entry:
|
||||||
|
; CHECK: test3:
|
||||||
|
; CHECK: revsh r0, r0
|
||||||
|
%0 = tail call i16 @llvm.bswap.i16(i16 %a)
|
||||||
|
%1 = sext i16 %0 to i32
|
||||||
|
ret i32 %1
|
||||||
|
}
|
||||||
|
|
||||||
|
declare i16 @llvm.bswap.i16(i16) nounwind readnone
|
||||||
|
|
||||||
|
define i32 @test4(i16 zeroext %a) nounwind {
|
||||||
|
entry:
|
||||||
|
; CHECK: test4:
|
||||||
|
; CHECK: revsh r0, r0
|
||||||
|
%conv = zext i16 %a to i32
|
||||||
|
%shr9 = lshr i16 %a, 8
|
||||||
|
%conv2 = zext i16 %shr9 to i32
|
||||||
|
%shl = shl nuw nsw i32 %conv, 8
|
||||||
|
%or = or i32 %conv2, %shl
|
||||||
|
%sext = shl i32 %or, 16
|
||||||
|
%conv8 = ashr exact i32 %sext, 16
|
||||||
|
ret i32 %conv8
|
||||||
|
}
|
Loading…
Reference in New Issue
Block a user