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[FastISel][X86] Use XOR to materialize the "0" value.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215594 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka 2014-08-13 22:22:17 +00:00
parent f245d9aa77
commit 0701e5d43b
5 changed files with 34 additions and 11 deletions
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23
lib/Target/X86/X86FastISel.cpp
View File

@ -3107,6 +3107,29 @@ unsigned X86FastISel::X86MaterializeInt(const ConstantInt *CI, MVT VT) {
return 0;
uint64_t Imm = CI->getZExtValue();
if (Imm == 0) {
unsigned SrcReg = FastEmitInst_(X86::MOV32r0, &X86::GR32RegClass);
switch (VT.SimpleTy) {
default: llvm_unreachable("Unexpected value type");
case MVT::i1:
case MVT::i8:
return FastEmitInst_extractsubreg(MVT::i8, SrcReg, /*Kill=*/true,
X86::sub_8bit);
case MVT::i16:
return FastEmitInst_extractsubreg(MVT::i16, SrcReg, /*Kill=*/true,
X86::sub_16bit);
case MVT::i32:
return SrcReg;
case MVT::i64: {
unsigned ResultReg = createResultReg(&X86::GR64RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg)
.addImm(0).addReg(SrcReg).addImm(X86::sub_32bit);
return ResultReg;
}
}
}
unsigned Opc = 0;
switch (VT.SimpleTy) {
default: llvm_unreachable("Unexpected value type");

10
test/CodeGen/X86/fast-isel-cmp-branch3.ll
View File

@ -351,7 +351,7 @@ bb1:
define i32 @icmp_eq(i32 %x) {
; CHECK-LABEL: icmp_eq
; CHECK-NOT: cmpl
; CHECK: movl $0, %eax
; CHECK: xorl %eax, %eax
%1 = icmp eq i32 %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@ -387,7 +387,7 @@ bb1:
define i32 @icmp_uge(i32 %x) {
; CHECK-LABEL: icmp_uge
; CHECK-NOT: cmpl
; CHECK: movl $0, %eax
; CHECK: xorl %eax, %eax
%1 = icmp uge i32 %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@ -411,7 +411,7 @@ bb1:
define i32 @icmp_ule(i32 %x) {
; CHECK-LABEL: icmp_ule
; CHECK-NOT: cmpl
; CHECK: movl $0, %eax
; CHECK: xorl %eax, %eax
%1 = icmp ule i32 %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@ -435,7 +435,7 @@ bb1:
define i32 @icmp_sge(i32 %x) {
; CHECK-LABEL: icmp_sge
; CHECK-NOT: cmpl
; CHECK: movl $0, %eax
; CHECK: xorl %eax, %eax
%1 = icmp sge i32 %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@ -459,7 +459,7 @@ bb1:
define i32 @icmp_sle(i32 %x) {
; CHECK-LABEL: icmp_sle
; CHECK-NOT: cmpl
; CHECK: movl $0, %eax
; CHECK: xorl %eax, %eax
%1 = icmp sle i32 %x, %x
br i1 %1, label %bb1, label %bb2
bb2:

4
test/CodeGen/X86/fast-isel-mem.ll
View File

@ -36,11 +36,11 @@ entry:
store i32 (...)** getelementptr ([4 x i32 (...)*]* @LotsStuff, i32 0, i32 2), i32 (...)*** null, align 4
ret void
; CHECK: _t:
; CHECK: movl $0, %eax
; CHECK: xorl %eax, %eax
; CHECK: movl L_LotsStuff$non_lazy_ptr, %ecx
; ATOM: _t:
; ATOM: movl L_LotsStuff$non_lazy_ptr, %e{{..}}
; ATOM: movl $0, %e{{..}}
; ATOM: xorl %e{{..}}, %e{{..}}
}

6
test/CodeGen/X86/fast-isel-x86-64.ll
View File

@ -144,7 +144,7 @@ if.end: ; preds = %if.then, %entry
; CHECK-LABEL: test12:
; CHECK: testb $1,
; CHECK-NEXT: je L
; CHECK-NEXT: movl $0, %edi
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: callq
}
@ -154,7 +154,7 @@ define void @test13() nounwind {
call void @test13f(i1 0)
ret void
; CHECK-LABEL: test13:
; CHECK: movl $0, %edi
; CHECK: xorl %edi, %edi
; CHECK-NEXT: callq
}
@ -278,7 +278,7 @@ entry:
call void @foo22(i32 3)
ret void
; CHECK-LABEL: test22:
; CHECK: movl $0, %edi
; CHECK: xorl %edi, %edi
; CHECK: callq _foo22
; CHECK: movl $1, %edi
; CHECK: callq _foo22

2
test/DebugInfo/X86/fission-ranges.ll
View File

@ -25,7 +25,7 @@
; if they've changed due to a bugfix, change in register allocation, etc.
; CHECK: [[A]]: Beginning address index: 2
; CHECK-NEXT: Length: 199
; CHECK-NEXT: Length: 190
; CHECK-NEXT: Location description: 11 00
; CHECK-NEXT: {{^$}}
; CHECK-NEXT: Beginning address index: 3