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[AArch64 neon] support poly64 and relevant intrinsic functions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194659 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Qin 2013-11-14 03:27:58 +00:00
parent 52301027aa
commit 0710afb9af
2 changed files with 12 additions and 0 deletions
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3
include/llvm/IR/IntrinsicsAArch64.td
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@ -325,6 +325,9 @@ def int_aarch64_neon_vshld_n : Neon_2Arg_ShiftImm_Intrinsic;
def int_aarch64_neon_vqshls_n : Neon_N2V_Intrinsic;
def int_aarch64_neon_vqshlu_n : Neon_N2V_Intrinsic;
// Scalar Signed Saturating Shift Left Unsigned (Immediate)
def int_aarch64_neon_vqshlus_n : Neon_N2V_Intrinsic;
// Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
def int_aarch64_neon_vcvtf32_n_s32 :
Intrinsic<[llvm_v1f32_ty], [llvm_v1i32_ty, llvm_i32_ty], [IntrNoMem]>;

9
lib/Target/AArch64/AArch64InstrNEON.td
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@ -4484,6 +4484,14 @@ defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrsqrte,
def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
class Neon_Scalar3Same_cmp_D_size_v1_patterns<SDPatternOperator opnode,
Instruction INSTD,
CondCode CC>
: Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm), CC)),
(INSTD FPR64:$Rn, FPR64:$Rm)>;
def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMEQddd, SETEQ>;
// Scalar Compare Signed Greather Than Or Equal
def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
@ -4503,6 +4511,7 @@ def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
// Scalar Compare Bitwise Test Bits
def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
def : Neon_Scalar3Same_cmp_D_size_patterns<Neon_tst, CMTSTddd>;
// Scalar Compare Bitwise Equal To Zero
def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;