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https://github.com/c64scene-ar/llvm-6502.git
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There is no need to emit a shift if the size is constant, which is common
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11420 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1198,21 +1198,29 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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}
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}
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// Turn the byte code into # iterations
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// Turn the byte code into # iterations
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unsigned ByteReg = getReg(CI.getOperand(3));
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unsigned ByteReg;
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unsigned CountReg;
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unsigned CountReg;
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switch (Align & 3) {
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switch (Align & 3) {
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case 2: // WORD aligned
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case 2: // WORD aligned
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if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
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CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
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} else {
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CountReg = makeAnotherReg(Type::IntTy);
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CountReg = makeAnotherReg(Type::IntTy);
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BuildMI(BB, X86::SHRir32, 2, CountReg).addReg(ByteReg).addZImm(1);
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BuildMI(BB, X86::SHRir32, 2, CountReg).addReg(ByteReg).addZImm(1);
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}
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break;
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break;
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case 0: // DWORD aligned
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case 0: // DWORD aligned
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if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
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CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
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} else {
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CountReg = makeAnotherReg(Type::IntTy);
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CountReg = makeAnotherReg(Type::IntTy);
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BuildMI(BB, X86::SHRir32, 2, CountReg).addReg(ByteReg).addZImm(2);
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BuildMI(BB, X86::SHRir32, 2, CountReg).addReg(ByteReg).addZImm(2);
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}
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break;
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break;
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case 1: // BYTE aligned
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case 1: // BYTE aligned
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case 3: // BYTE aligned
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case 3: // BYTE aligned
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CountReg = ByteReg;
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CountReg = getReg(CI.getOperand(3));
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break;
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break;
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}
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}
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@ -1224,7 +1232,6 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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BuildMI(BB, X86::MOVrr32, 1, X86::EDI).addReg(TmpReg1);
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BuildMI(BB, X86::MOVrr32, 1, X86::EDI).addReg(TmpReg1);
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BuildMI(BB, X86::MOVrr32, 1, X86::ESI).addReg(TmpReg2);
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BuildMI(BB, X86::MOVrr32, 1, X86::ESI).addReg(TmpReg2);
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unsigned Bytes = getReg(CI.getOperand(3));
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switch (Align & 3) {
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switch (Align & 3) {
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case 1: // BYTE aligned
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case 1: // BYTE aligned
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case 3: // BYTE aligned
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case 3: // BYTE aligned
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@ -1198,21 +1198,29 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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}
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}
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// Turn the byte code into # iterations
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// Turn the byte code into # iterations
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unsigned ByteReg = getReg(CI.getOperand(3));
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unsigned ByteReg;
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unsigned CountReg;
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unsigned CountReg;
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switch (Align & 3) {
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switch (Align & 3) {
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case 2: // WORD aligned
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case 2: // WORD aligned
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if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
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CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
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} else {
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CountReg = makeAnotherReg(Type::IntTy);
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CountReg = makeAnotherReg(Type::IntTy);
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BuildMI(BB, X86::SHRir32, 2, CountReg).addReg(ByteReg).addZImm(1);
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BuildMI(BB, X86::SHRir32, 2, CountReg).addReg(ByteReg).addZImm(1);
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}
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break;
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break;
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case 0: // DWORD aligned
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case 0: // DWORD aligned
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if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
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CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
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} else {
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CountReg = makeAnotherReg(Type::IntTy);
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CountReg = makeAnotherReg(Type::IntTy);
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BuildMI(BB, X86::SHRir32, 2, CountReg).addReg(ByteReg).addZImm(2);
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BuildMI(BB, X86::SHRir32, 2, CountReg).addReg(ByteReg).addZImm(2);
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}
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break;
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break;
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case 1: // BYTE aligned
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case 1: // BYTE aligned
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case 3: // BYTE aligned
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case 3: // BYTE aligned
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CountReg = ByteReg;
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CountReg = getReg(CI.getOperand(3));
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break;
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break;
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}
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}
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@ -1224,7 +1232,6 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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BuildMI(BB, X86::MOVrr32, 1, X86::EDI).addReg(TmpReg1);
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BuildMI(BB, X86::MOVrr32, 1, X86::EDI).addReg(TmpReg1);
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BuildMI(BB, X86::MOVrr32, 1, X86::ESI).addReg(TmpReg2);
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BuildMI(BB, X86::MOVrr32, 1, X86::ESI).addReg(TmpReg2);
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unsigned Bytes = getReg(CI.getOperand(3));
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switch (Align & 3) {
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switch (Align & 3) {
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case 1: // BYTE aligned
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case 1: // BYTE aligned
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case 3: // BYTE aligned
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case 3: // BYTE aligned
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