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Add patterns for converting stores of subvector_extracts of lower 128-bits of a 256-bit vector to VMOVAPSmr/VMOVUPSmr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163292 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1019,6 +1019,46 @@ let Predicates = [HasAVX] in {
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(VMOVUPSYmr addr:$dst, VR256:$src)>;
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def : Pat<(store (v32i8 VR256:$src), addr:$dst),
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(VMOVUPSYmr addr:$dst, VR256:$src)>;
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// Special patterns for storing subvector extracts of lower 128-bits
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// Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
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def : Pat<(alignedstore (v2f64 (extract_subvector
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(v4f64 VR256:$src), (i32 0))), addr:$dst),
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(VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(alignedstore (v4f32 (extract_subvector
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(v8f32 VR256:$src), (i32 0))), addr:$dst),
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(VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(alignedstore (v2i64 (extract_subvector
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(v4i64 VR256:$src), (i32 0))), addr:$dst),
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(VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(alignedstore (v4i32 (extract_subvector
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(v8i32 VR256:$src), (i32 0))), addr:$dst),
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(VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(alignedstore (v8i16 (extract_subvector
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(v16i16 VR256:$src), (i32 0))), addr:$dst),
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(VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(alignedstore (v16i8 (extract_subvector
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(v32i8 VR256:$src), (i32 0))), addr:$dst),
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(VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v2f64 (extract_subvector
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(v4f64 VR256:$src), (i32 0))), addr:$dst),
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(VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v4f32 (extract_subvector
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(v8f32 VR256:$src), (i32 0))), addr:$dst),
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(VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v2i64 (extract_subvector
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(v4i64 VR256:$src), (i32 0))), addr:$dst),
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(VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v4i32 (extract_subvector
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(v8i32 VR256:$src), (i32 0))), addr:$dst),
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(VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v8i16 (extract_subvector
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(v16i16 VR256:$src), (i32 0))), addr:$dst),
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(VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v16i8 (extract_subvector
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(v32i8 VR256:$src), (i32 0))), addr:$dst),
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(VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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}
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// Use movaps / movups for SSE integer load / store (one byte shorter).
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@ -19,12 +19,12 @@ entry:
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}
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; CHECK: @t0
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; CHECK-NOT: vextractf128 $0, %ymm0, %xmm0
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; CHECK-NOT: vextractf128 $1, %ymm0, %xmm0
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; CHECK-NOT: vmovaps %xmm0, (%rdi)
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; CHECK: vextractf128 $0, %ymm0, (%rdi)
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; CHECK: vextractf128 $1, %ymm0, (%rdi)
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define void @t0(float* nocapture %addr, <8 x float> %a) nounwind uwtable ssp {
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entry:
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%0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %a, i8 0)
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%0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %a, i8 1)
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%1 = bitcast float* %addr to <4 x float>*
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store <4 x float> %0, <4 x float>* %1, align 16
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ret void
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@ -33,12 +33,12 @@ entry:
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declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone
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; CHECK: @t2
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; CHECK-NOT: vextractf128 $0, %ymm0, %xmm0
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; CHECK-NOT: vextractf128 $1, %ymm0, %xmm0
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; CHECK-NOT: vmovaps %xmm0, (%rdi)
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; CHECK: vextractf128 $0, %ymm0, (%rdi)
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; CHECK: vextractf128 $1, %ymm0, (%rdi)
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define void @t2(double* nocapture %addr, <4 x double> %a) nounwind uwtable ssp {
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entry:
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%0 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a, i8 0)
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%0 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a, i8 1)
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%1 = bitcast double* %addr to <2 x double>*
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store <2 x double> %0, <2 x double>* %1, align 16
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ret void
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@ -47,10 +47,43 @@ entry:
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declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone
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; CHECK: @t4
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; CHECK-NOT: vextractf128 $0, %ymm0, %xmm0
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; CHECK-NOT: vextractf128 $1, %ymm0, %xmm0
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; CHECK-NOT: vmovaps %xmm0, (%rdi)
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; CHECK: vextractf128 $0, %ymm0, (%rdi)
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; CHECK: vextractf128 $1, %ymm0, (%rdi)
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define void @t4(<2 x i64>* nocapture %addr, <4 x i64> %a) nounwind uwtable ssp {
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entry:
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%0 = bitcast <4 x i64> %a to <8 x i32>
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%1 = tail call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %0, i8 1)
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%2 = bitcast <4 x i32> %1 to <2 x i64>
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store <2 x i64> %2, <2 x i64>* %addr, align 16
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ret void
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}
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declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind readnone
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; CHECK: @t5
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; CHECK: vmovaps %xmm0, (%rdi)
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define void @t5(float* nocapture %addr, <8 x float> %a) nounwind uwtable ssp {
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entry:
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%0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %a, i8 0)
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%1 = bitcast float* %addr to <4 x float>*
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store <4 x float> %0, <4 x float>* %1, align 16
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ret void
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}
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; CHECK: @t6
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; CHECK: vmovaps %xmm0, (%rdi)
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define void @t6(double* nocapture %addr, <4 x double> %a) nounwind uwtable ssp {
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entry:
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%0 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a, i8 0)
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%1 = bitcast double* %addr to <2 x double>*
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store <2 x double> %0, <2 x double>* %1, align 16
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ret void
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}
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; CHECK: @t7
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; CHECK: vmovaps %xmm0, (%rdi)
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define void @t7(<2 x i64>* nocapture %addr, <4 x i64> %a) nounwind uwtable ssp {
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entry:
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%0 = bitcast <4 x i64> %a to <8 x i32>
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%1 = tail call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %0, i8 0)
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@ -59,4 +92,13 @@ entry:
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ret void
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}
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declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind readnone
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; CHECK: @t8
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; CHECK: vmovups %xmm0, (%rdi)
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define void @t8(<2 x i64>* nocapture %addr, <4 x i64> %a) nounwind uwtable ssp {
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entry:
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%0 = bitcast <4 x i64> %a to <8 x i32>
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%1 = tail call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %0, i8 0)
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%2 = bitcast <4 x i32> %1 to <2 x i64>
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store <2 x i64> %2, <2 x i64>* %addr, align 1
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ret void
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}
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