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Unify handling of constant pool indexes with the other code paths, allowing
us to use index registers for CPI's git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17082 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -385,24 +385,24 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI,
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DispVal = Op3.getImmedValue();
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}
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if (MI.getOperand(Op).isConstantPoolIndex()) {
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// Emit a direct address reference [disp32] where the displacement of the
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// constant pool entry is controlled by the MCE.
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assert(!GV && "Constant Pool reference cannot be relative to global!");
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
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unsigned Index = MI.getOperand(Op).getConstantPoolIndex();
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unsigned Address = MCE.getConstantPoolEntryAddress(Index);
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MCE.emitWord(Address+DispVal);
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return;
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}
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const MachineOperand &BaseReg = MI.getOperand(Op);
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const MachineOperand &Base = MI.getOperand(Op);
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const MachineOperand &Scale = MI.getOperand(Op+1);
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const MachineOperand &IndexReg = MI.getOperand(Op+2);
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unsigned BaseReg = 0;
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if (Base.isConstantPoolIndex()) {
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// Emit a direct address reference [disp32] where the displacement of the
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// constant pool entry is controlled by the MCE.
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assert(!GV && "Constant Pool reference cannot be relative to global!");
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DispVal += MCE.getConstantPoolEntryAddress(Base.getConstantPoolIndex());
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} else {
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BaseReg = Base.getReg();
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}
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// Is a SIB byte needed?
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if (IndexReg.getReg() == 0 && BaseReg.getReg() != X86::ESP) {
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if (BaseReg.getReg() == 0) { // Just a displacement?
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if (IndexReg.getReg() == 0 && BaseReg != X86::ESP) {
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if (BaseReg == 0) { // Just a displacement?
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// Emit special case [disp32] encoding
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
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if (GV)
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@ -410,7 +410,7 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI,
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else
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emitConstant(DispVal, 4);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
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unsigned BaseRegNo = getX86RegNum(BaseReg);
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if (GV) {
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// Emit the most general non-SIB encoding: [REG+disp32]
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MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
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@ -434,7 +434,7 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI,
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bool ForceDisp32 = false;
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bool ForceDisp8 = false;
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if (BaseReg.getReg() == 0) {
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if (BaseReg == 0) {
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// If there is no base register, we emit the special case SIB byte with
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// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
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@ -443,7 +443,7 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI,
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// Emit the normal disp32 encoding...
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MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
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ForceDisp32 = true;
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} else if (DispVal == 0 && BaseReg.getReg() != X86::EBP) {
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} else if (DispVal == 0 && BaseReg != X86::EBP) {
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// Emit no displacement ModR/M byte
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
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} else if (isDisp8(DispVal)) {
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@ -459,13 +459,13 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI,
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static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
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unsigned SS = SSTable[Scale.getImmedValue()];
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if (BaseReg.getReg() == 0) {
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if (BaseReg == 0) {
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// Handle the SIB byte for the case where there is no base. The
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// displacement has already been output.
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assert(IndexReg.getReg() && "Index register must be specified!");
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emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
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unsigned BaseRegNo = getX86RegNum(BaseReg);
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unsigned IndexRegNo;
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if (IndexReg.getReg())
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IndexRegNo = getX86RegNum(IndexReg.getReg());
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