6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-15 07:34:33 +00:00
Code Issues Projects Releases Wiki Activity

R600: Change how vector truncating stores are packed.

Browse Source 
Don't introduce new operations on an illegal sub 32-bit type.
Do the operations on a 32-bit value, and then use a truncating store.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206864 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-04-22 04:11:14 +00:00
parent 3ddf868b04
commit 073440f3d4
1 changed files with 25 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
lib/Target/R600/AMDGPUISelLowering.cpp
View File

@ -685,32 +685,46 @@ SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
} }
SDLoc DL(Op); SDLoc DL(Op);
const SDValue &Value = Store->getValue(); SDValue Value = Store->getValue();
EVT VT = Value.getValueType(); EVT VT = Value.getValueType();
const SDValue &Ptr = Store->getBasePtr(); EVT ElemVT = VT.getVectorElementType();
SDValue Ptr = Store->getBasePtr();
EVT MemEltVT = MemVT.getVectorElementType(); EVT MemEltVT = MemVT.getVectorElementType();
unsigned MemEltBits = MemEltVT.getSizeInBits(); unsigned MemEltBits = MemEltVT.getSizeInBits();
unsigned MemNumElements = MemVT.getVectorNumElements(); unsigned MemNumElements = MemVT.getVectorNumElements();
EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits()); unsigned PackedSize = MemVT.getStoreSizeInBits();
SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, PackedVT); SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
assert(Value.getValueType().getScalarSizeInBits() >= 32);
SDValue PackedValue; SDValue PackedValue;
for (unsigned i = 0; i < MemNumElements; ++i) { for (unsigned i = 0; i < MemNumElements; ++i) {
EVT ElemVT = VT.getVectorElementType();
SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value, SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
DAG.getConstant(i, MVT::i32)); DAG.getConstant(i, MVT::i32));
Elt = DAG.getZExtOrTrunc(Elt, DL, PackedVT); Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
Elt = DAG.getNode(ISD::AND, DL, PackedVT, Elt, Mask); Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
SDValue Shift = DAG.getConstant(MemEltBits * i, PackedVT);
Elt = DAG.getNode(ISD::SHL, DL, PackedVT, Elt, Shift); SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
if (i == 0) { if (i == 0) {
PackedValue = Elt; PackedValue = Elt;
} else { } else {
PackedValue = DAG.getNode(ISD::OR, DL, PackedVT, PackedValue, Elt); PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
} }
} }
if (PackedSize < 32) {
EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
Store->getMemOperand()->getPointerInfo(),
PackedVT,
Store->isNonTemporal(), Store->isVolatile(),
Store->getAlignment());
}
return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr, return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
MachinePointerInfo(Store->getMemOperand()->getValue()), Store->getMemOperand()->getPointerInfo(),
Store->isVolatile(), Store->isNonTemporal(), Store->isVolatile(), Store->isNonTemporal(),
Store->getAlignment()); Store->getAlignment());
} }