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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Minor cleanup. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48142 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -50,8 +50,7 @@ namespace {
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual bool runOnMachineFunction(MachineFunction &MF);
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/// FIXME: Loop preheaders?
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// FIXME: Loop preheaders?
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///
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.setPreservesCFG();
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AU.addRequired<MachineLoopInfo>();
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AU.addRequired<MachineLoopInfo>();
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@ -119,6 +118,9 @@ namespace {
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if (ToMBB->getBasicBlock())
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if (ToMBB->getBasicBlock())
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DOUT << " to MachineBasicBlock "
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DOUT << " to MachineBasicBlock "
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<< ToMBB->getBasicBlock()->getName();
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<< ToMBB->getBasicBlock()->getName();
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if (FromMBB->getBasicBlock())
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DOUT << " from MachineBasicBlock "
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<< FromMBB->getBasicBlock()->getName();
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DOUT << "\n";
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DOUT << "\n";
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});
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});
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@ -241,8 +243,7 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
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return false;
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return false;
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}
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}
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}
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}
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DEBUG({
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DEBUG({
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DOUT << "--- Checking if we can hoist " << I;
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DOUT << "--- Checking if we can hoist " << I;
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if (I.getDesc().getImplicitUses()) {
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if (I.getDesc().getImplicitUses()) {
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@ -271,13 +272,14 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
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for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
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for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = I.getOperand(i);
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const MachineOperand &MO = I.getOperand(i);
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if (!(MO.isRegister() && MO.getReg() && MO.isUse()))
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if (!MO.isRegister() || !MO.isUse())
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continue;
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continue;
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unsigned Reg = MO.getReg();
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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// Don't hoist instructions that access physical registers.
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// Don't hoist instructions that access physical registers.
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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return false;
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return false;
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assert(RegInfo->getVRegDef(Reg)&&"Machine instr not mapped for this vreg?");
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assert(RegInfo->getVRegDef(Reg)&&"Machine instr not mapped for this vreg?");
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