Minor cleanup. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48142 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2008-03-10 08:13:01 +00:00
parent 4ff3f1cc57
commit 074223a124

View File

@ -50,8 +50,7 @@ namespace {
virtual bool runOnMachineFunction(MachineFunction &MF); virtual bool runOnMachineFunction(MachineFunction &MF);
/// FIXME: Loop preheaders? // FIXME: Loop preheaders?
///
virtual void getAnalysisUsage(AnalysisUsage &AU) const { virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG(); AU.setPreservesCFG();
AU.addRequired<MachineLoopInfo>(); AU.addRequired<MachineLoopInfo>();
@ -119,6 +118,9 @@ namespace {
if (ToMBB->getBasicBlock()) if (ToMBB->getBasicBlock())
DOUT << " to MachineBasicBlock " DOUT << " to MachineBasicBlock "
<< ToMBB->getBasicBlock()->getName(); << ToMBB->getBasicBlock()->getName();
if (FromMBB->getBasicBlock())
DOUT << " from MachineBasicBlock "
<< FromMBB->getBasicBlock()->getName();
DOUT << "\n"; DOUT << "\n";
}); });
@ -241,8 +243,7 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
return false; return false;
} }
} }
DEBUG({ DEBUG({
DOUT << "--- Checking if we can hoist " << I; DOUT << "--- Checking if we can hoist " << I;
if (I.getDesc().getImplicitUses()) { if (I.getDesc().getImplicitUses()) {
@ -271,13 +272,14 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = I.getOperand(i); const MachineOperand &MO = I.getOperand(i);
if (!(MO.isRegister() && MO.getReg() && MO.isUse())) if (!MO.isRegister() || !MO.isUse())
continue; continue;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (Reg == 0) continue;
// Don't hoist instructions that access physical registers. // Don't hoist instructions that access physical registers.
if (!TargetRegisterInfo::isVirtualRegister(Reg)) if (TargetRegisterInfo::isPhysicalRegister(Reg))
return false; return false;
assert(RegInfo->getVRegDef(Reg)&&"Machine instr not mapped for this vreg?"); assert(RegInfo->getVRegDef(Reg)&&"Machine instr not mapped for this vreg?");