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https://github.com/c64scene-ar/llvm-6502.git
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Merge more SSE/AVX instruction definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171102 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
fc093def2d
commit
07555fc640
@ -2657,10 +2657,8 @@ let ExeDomain = SSEPackedInt in { // SSE integer instructions
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/// PDI_binop_rm - Simple SSE2 binary operator.
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/// PDI_binop_rm - Simple SSE2 binary operator.
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multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
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ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
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X86MemOperand x86memop,
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X86MemOperand x86memop, OpndItins itins,
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OpndItins itins,
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bit IsCommutable, bit Is2Addr> {
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bit IsCommutable = 0,
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bit Is2Addr = 1> {
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let isCommutable = IsCommutable in
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let isCommutable = IsCommutable in
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def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
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def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2),
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(ins RC:$src1, RC:$src2),
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@ -2688,7 +2686,7 @@ let Predicates = [HasAVX] in
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let Constraints = "$src1 = $dst" in
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let Constraints = "$src1 = $dst" in
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defm P#NAME# : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
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defm P#NAME# : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
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memopv2i64, i128mem, itins, IsCommutable>;
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memopv2i64, i128mem, itins, IsCommutable, 1>;
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let Predicates = [HasAVX2] in
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let Predicates = [HasAVX2] in
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defm VP#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
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defm VP#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
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@ -3630,6 +3628,24 @@ multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
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itins.rm>;
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itins.rm>;
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}
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}
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multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
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Intrinsic IntId256, OpndItins itins,
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bit IsCommutable = 0> {
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let Predicates = [HasAVX] in
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defm VP#NAME# : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
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VR128, memopv2i64, i128mem, itins,
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IsCommutable, 0>, VEX_4V;
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let Constraints = "$src1 = $dst" in
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defm P#NAME# : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
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i128mem, itins, IsCommutable, 1>;
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let Predicates = [HasAVX2] in
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defm VP#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
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VR256, memopv4i64, i256mem, itins,
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IsCommutable, 0>, VEX_4V, VEX_L;
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}
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multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
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multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
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string OpcodeStr, SDNode OpNode,
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string OpcodeStr, SDNode OpNode,
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SDNode OpNode2, RegisterClass RC,
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SDNode OpNode2, RegisterClass RC,
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@ -3713,140 +3729,44 @@ defm MAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
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defm MAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
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defm MAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
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SSE_INTALU_ITINS_P, 1>;
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SSE_INTALU_ITINS_P, 1>;
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// 128-bit Integer Arithmetic
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// Intrinsic forms
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defm SUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
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int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
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defm SUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
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int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
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defm ADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
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int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
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defm ADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
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int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
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defm ADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
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int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
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defm ADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
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int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
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defm MULHUW : PDI_binop_all_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
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int_x86_avx2_pmulhu_w, SSE_INTMUL_ITINS_P, 1>;
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defm MULHW : PDI_binop_all_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
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int_x86_avx2_pmulh_w, SSE_INTMUL_ITINS_P, 1>;
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defm MADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
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int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
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defm AVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
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int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
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defm AVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
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int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
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defm SADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
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int_x86_avx2_psad_bw, SSE_INTALU_ITINS_P, 1>;
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let Predicates = [HasAVX] in {
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let Predicates = [HasAVX] in
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defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
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defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
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memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
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memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
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VEX_4V;
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VEX_4V;
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let Predicates = [HasAVX2] in
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// Intrinsic forms
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defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
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defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
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defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
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defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
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defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
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defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
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defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
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VR128, memopv2i64, i128mem,
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SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
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defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
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VR128, memopv2i64, i128mem,
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SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
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defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
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VR128, memopv2i64, i128mem,
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SSE_PMADD, 1, 0>, VEX_4V;
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defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
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defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
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defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
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}
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let Predicates = [HasAVX2] in {
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defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
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defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
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VR256, memopv4i64, i256mem,
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VR256, memopv4i64, i256mem,
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SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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let Constraints = "$src1 = $dst" in
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// Intrinsic forms
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defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
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VR256, memopv4i64, i256mem,
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SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
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defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
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VR256, memopv4i64, i256mem,
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SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
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defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
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VR256, memopv4i64, i256mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
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VR256, memopv4i64, i256mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
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VR256, memopv4i64, i256mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
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VR256, memopv4i64, i256mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
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VR256, memopv4i64, i256mem,
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SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
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VR256, memopv4i64, i256mem,
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SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
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VR256, memopv4i64, i256mem,
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SSE_PMADD, 1, 0>, VEX_4V, VEX_L;
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defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
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VR256, memopv4i64, i256mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
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VR256, memopv4i64, i256mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
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VR256, memopv4i64, i256mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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}
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let Constraints = "$src1 = $dst" in {
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defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
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defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
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memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
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memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
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// Intrinsic forms
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defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P>;
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defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P>;
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defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P, 1>;
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defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P, 1>;
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defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P, 1>;
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defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P, 1>;
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defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
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VR128, memopv2i64, i128mem,
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SSE_INTMUL_ITINS_P, 1>;
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defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
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VR128, memopv2i64, i128mem,
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SSE_INTMUL_ITINS_P, 1>;
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defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
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VR128, memopv2i64, i128mem,
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SSE_PMADD, 1>;
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defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P, 1>;
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defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P, 1>;
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defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P, 1>;
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} // Constraints = "$src1 = $dst"
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//===---------------------------------------------------------------------===//
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//===---------------------------------------------------------------------===//
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// SSE2 - Packed Integer Logical Instructions
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// SSE2 - Packed Integer Logical Instructions
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//===---------------------------------------------------------------------===//
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//===---------------------------------------------------------------------===//
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