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https://github.com/c64scene-ar/llvm-6502.git
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Add support for 256-bit versions of VSHUFPD and VSHUFPS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138546 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
e7461c0353
commit
07b7f672a0
@ -3178,6 +3178,152 @@ static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
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return true;
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}
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/// isVSHUFPSYMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to 256-bit
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/// VSHUFPSY.
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static bool isVSHUFPSYMask(const SmallVectorImpl<int> &Mask, EVT VT,
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const X86Subtarget *Subtarget) {
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int NumElems = VT.getVectorNumElements();
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if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
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return false;
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if (NumElems != 8)
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return false;
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// VSHUFPSY divides the resulting vector into 4 chunks.
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// The sources are also splitted into 4 chunks, and each destination
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// chunk must come from a different source chunk.
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//
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// SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
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// SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
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//
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// DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
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// Y3..Y0, Y3..Y0, X3..X0, X3..X0
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//
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int QuarterSize = NumElems/4;
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int HalfSize = QuarterSize*2;
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for (int i = 0; i < QuarterSize; ++i)
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if (!isUndefOrInRange(Mask[i], 0, HalfSize))
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return false;
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for (int i = QuarterSize; i < QuarterSize*2; ++i)
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if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
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return false;
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// The mask of the second half must be the same as the first but with
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// the appropriate offsets. This works in the same way as VPERMILPS
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// works with masks.
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for (int i = QuarterSize*2; i < QuarterSize*3; ++i) {
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if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
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return false;
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int FstHalfIdx = i-HalfSize;
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if (Mask[FstHalfIdx] < 0)
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continue;
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if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
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return false;
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}
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for (int i = QuarterSize*3; i < NumElems; ++i) {
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if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
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return false;
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int FstHalfIdx = i-HalfSize;
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if (Mask[FstHalfIdx] < 0)
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continue;
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if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
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return false;
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}
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return true;
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}
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/// getShuffleVSHUFPSYImmediate - Return the appropriate immediate to shuffle
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/// the specified VECTOR_MASK mask with VSHUFPSY instruction.
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static unsigned getShuffleVSHUFPSYImmediate(SDNode *N) {
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
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EVT VT = SVOp->getValueType(0);
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int NumElems = VT.getVectorNumElements();
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assert(NumElems == 8 && VT.getSizeInBits() == 256 &&
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"Only supports v8i32 and v8f32 types");
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int HalfSize = NumElems/2;
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unsigned Mask = 0;
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for (int i = 0; i != NumElems ; ++i) {
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if (SVOp->getMaskElt(i) < 0)
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continue;
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// The mask of the first half must be equal to the second one.
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unsigned Shamt = (i%HalfSize)*2;
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unsigned Elt = SVOp->getMaskElt(i) % HalfSize;
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Mask |= Elt << Shamt;
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}
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return Mask;
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}
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/// isVSHUFPDYMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to 256-bit
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/// VSHUFPDY. This shuffle doesn't have the same restriction as the PS
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/// version and the mask of the second half isn't binded with the first
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/// one.
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static bool isVSHUFPDYMask(const SmallVectorImpl<int> &Mask, EVT VT,
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const X86Subtarget *Subtarget) {
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int NumElems = VT.getVectorNumElements();
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if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
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return false;
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if (NumElems != 4)
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return false;
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// VSHUFPSY divides the resulting vector into 4 chunks.
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// The sources are also splitted into 4 chunks, and each destination
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// chunk must come from a different source chunk.
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//
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// SRC1 => X3 X2 X1 X0
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// SRC2 => Y3 Y2 Y1 Y0
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//
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// DST => Y2..Y3, X2..X3, Y1..Y0, X1..X0
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//
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int QuarterSize = NumElems/4;
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int HalfSize = QuarterSize*2;
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for (int i = 0; i < QuarterSize; ++i)
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if (!isUndefOrInRange(Mask[i], 0, HalfSize))
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return false;
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for (int i = QuarterSize; i < QuarterSize*2; ++i)
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if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
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return false;
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for (int i = QuarterSize*2; i < QuarterSize*3; ++i)
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if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
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return false;
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for (int i = QuarterSize*3; i < NumElems; ++i)
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if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
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return false;
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return true;
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}
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/// getShuffleVSHUFPDYImmediate - Return the appropriate immediate to shuffle
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/// the specified VECTOR_MASK mask with VSHUFPDY instruction.
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static unsigned getShuffleVSHUFPDYImmediate(SDNode *N) {
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
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EVT VT = SVOp->getValueType(0);
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int NumElems = VT.getVectorNumElements();
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assert(NumElems == 4 && VT.getSizeInBits() == 256 &&
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"Only supports v4i64 and v4f64 types");
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int HalfSize = NumElems/2;
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unsigned Mask = 0;
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for (int i = 0; i != NumElems ; ++i) {
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if (SVOp->getMaskElt(i) < 0)
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continue;
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int Elt = SVOp->getMaskElt(i) % HalfSize;
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Mask |= Elt << i;
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}
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return Mask;
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}
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/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to 128-bit
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/// SHUFPS and SHUFPD.
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@ -6068,6 +6214,22 @@ SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
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return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
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}
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static inline unsigned getSHUFPOpcode(EVT VT) {
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switch(VT.getSimpleVT().SimpleTy) {
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case MVT::v8i32: // Use fp unit for int unpack.
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case MVT::v8f32:
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case MVT::v4i32: // Use fp unit for int unpack.
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case MVT::v4f32: return X86ISD::SHUFPS;
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case MVT::v4i64: // Use fp unit for int unpack.
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case MVT::v4f64:
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case MVT::v2i64: // Use fp unit for int unpack.
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case MVT::v2f64: return X86ISD::SHUFPD;
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default:
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llvm_unreachable("Unknown type for shufp*");
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}
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return 0;
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}
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static
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SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
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SDValue V1 = Op.getOperand(0);
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@ -6121,7 +6283,7 @@ SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
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assert(VT != MVT::v4i32 && "unsupported shuffle type");
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// Invert the operand order and use SHUFPS to match it.
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return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
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return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1,
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X86::getShuffleSHUFImmediate(SVOp), DAG);
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}
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@ -6357,13 +6519,8 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
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return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
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if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
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return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1,
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TargetMask, DAG);
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if (VT == MVT::v4f32)
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return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1,
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TargetMask, DAG);
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return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1,
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TargetMask, DAG);
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}
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// Check if this can be converted into a logical shift.
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@ -6515,15 +6672,9 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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X86::getShufflePSHUFLWImmediate(SVOp),
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DAG);
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if (isSHUFPMask(M, VT)) {
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unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
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if (VT == MVT::v4f32 || VT == MVT::v4i32)
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return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2,
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TargetMask, DAG);
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if (VT == MVT::v2f64 || VT == MVT::v2i64)
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return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2,
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TargetMask, DAG);
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}
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if (isSHUFPMask(M, VT))
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return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
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X86::getShuffleSHUFImmediate(SVOp), DAG);
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if (X86::isUNPCKL_v_undef_Mask(SVOp))
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return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
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@ -6550,6 +6701,16 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2,
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getShuffleVPERM2F128Immediate(SVOp), DAG);
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// Handle VSHUFPSY permutations
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if (isVSHUFPSYMask(M, VT, Subtarget))
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return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
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getShuffleVSHUFPSYImmediate(SVOp), DAG);
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// Handle VSHUFPDY permutations
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if (isVSHUFPDYMask(M, VT, Subtarget))
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return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
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getShuffleVSHUFPDYImmediate(SVOp), DAG);
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//===--------------------------------------------------------------------===//
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// Since no target specific shuffle was selected for this generic one,
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// lower it into other known shuffles. FIXME: this isn't true yet, but
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@ -1709,7 +1709,7 @@ let Predicates = [HasAVX] in {
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def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
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(VSHUFPDrri VR128:$src1, VR128:$src2,
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(SHUFFLE_get_shuf_imm VR128:$src3))>;
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// Generic VSHUFPD patterns
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def : Pat<(v2f64 (X86Shufps VR128:$src1,
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(memopv2f64 addr:$src2), (i8 imm:$imm))),
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(VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
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@ -1717,6 +1717,31 @@ let Predicates = [HasAVX] in {
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(VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
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def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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(VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
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// 256-bit patterns
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def : Pat<(v8i32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
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(VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
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def : Pat<(v8i32 (X86Shufps VR256:$src1,
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(bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
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(VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
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def : Pat<(v8f32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
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(VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
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def : Pat<(v8f32 (X86Shufps VR256:$src1,
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(memopv8f32 addr:$src2), (i8 imm:$imm))),
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(VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
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def : Pat<(v4i64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
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(VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
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def : Pat<(v4i64 (X86Shufpd VR256:$src1,
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(memopv4i64 addr:$src2), (i8 imm:$imm))),
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(VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
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def : Pat<(v4f64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
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(VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
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def : Pat<(v4f64 (X86Shufpd VR256:$src1,
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(memopv4f64 addr:$src2), (i8 imm:$imm))),
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(VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
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}
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//===----------------------------------------------------------------------===//
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@ -64,10 +64,8 @@ entry:
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ret <4 x i64> %shuffle
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}
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; CHECK: vpunpckhqdq
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; CHECK-NEXT: vextractf128 $1
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; CHECK-NEXT: movlhps
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; CHECK-NEXT: vinsertf128 $1
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; CHECK: _B
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; CHECK: vshufpd $1, %ymm
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define <4 x i64> @B(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 undef, i32 undef, i32 6>
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29
test/CodeGen/X86/avx-vshufp.ll
Normal file
29
test/CodeGen/X86/avx-vshufp.ll
Normal file
@ -0,0 +1,29 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; CHECK: vshufps $-53, %ymm
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define <8 x float> @A(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 3, i32 2, i32 8, i32 11, i32 7, i32 6, i32 12, i32 15>
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ret <8 x float> %shuffle
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}
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; CHECK: vshufpd $10, %ymm
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define <4 x double> @B(<4 x double> %a, <4 x double> %b) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x double> %shuffle
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}
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; CHECK: vshufps $-53, %ymm
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define <8 x float> @C(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 3, i32 undef, i32 undef, i32 11, i32 undef, i32 6, i32 12, i32 undef>
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ret <8 x float> %shuffle
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}
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; CHECK: vshufpd $2, %ymm
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define <4 x double> @D(<4 x double> %a, <4 x double> %b) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 undef>
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ret <4 x double> %shuffle
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}
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