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Scalar f32/f64 are also subregs of ymm regs

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120844 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2010-12-03 21:54:39 +00:00
parent 163e83d69a
commit 07c21d85b4
1 changed files with 6 additions and 0 deletions
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6
lib/Target/X86/X86InstrSSE.td
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@ -180,6 +180,12 @@ def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
// Implicitly promote a 64-bit scalar to a vector. // Implicitly promote a 64-bit scalar to a vector.
def : Pat<(v2f64 (scalar_to_vector FR64:$src)), def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>; (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
// Implicitly promote a 32-bit scalar to a vector.
def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
(INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
// Implicitly promote a 64-bit scalar to a vector.
def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
(INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
let AddedComplexity = 20 in { let AddedComplexity = 20 in {
// MOVSSrm zeros the high parts of the register; represent this // MOVSSrm zeros the high parts of the register; represent this