mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-06 06:33:24 +00:00
Remove the hidden "neon-reg-sequence" option. The reg sequences are working
now, so there's no need to disable them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106155 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
parent
bc06737c35
commit
07f6e805b1
@ -90,10 +90,6 @@ inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
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}
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}
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/// ModelWithRegSequence - Return true if isel should use REG_SEQUENCE to model
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/// operations involving sub-registers.
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bool ModelWithRegSequence();
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FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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@ -36,11 +36,6 @@
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using namespace llvm;
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static cl::opt<bool>
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UseRegSeq("neon-reg-sequence", cl::Hidden,
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cl::desc("Use reg_sequence to model ld / st of multiple neon regs"),
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cl::init(true));
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//===--------------------------------------------------------------------===//
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/// ARMDAGToDAGISel - ARM specific code to select ARM machine
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/// instructions for SelectionDAG operations.
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@ -962,17 +957,9 @@ SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
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DebugLoc dl = V0.getNode()->getDebugLoc();
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SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
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SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
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if (llvm::ModelWithRegSequence()) {
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const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
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}
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SDValue Undef =
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SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0);
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SDNode *Pair = CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
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VT, Undef, V0, SubReg0);
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return CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
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VT, SDValue(Pair, 0), V1, SubReg1);
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}
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/// PairDRegs - Form a quad register from a pair of D registers.
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///
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@ -980,17 +967,9 @@ SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
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DebugLoc dl = V0.getNode()->getDebugLoc();
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SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
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SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
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if (llvm::ModelWithRegSequence()) {
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const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
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}
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SDValue Undef =
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SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0);
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SDNode *Pair = CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
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VT, Undef, V0, SubReg0);
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return CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
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VT, SDValue(Pair, 0), V1, SubReg1);
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}
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/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
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///
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@ -1115,7 +1094,7 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
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std::vector<EVT> ResTys(NumVecs, VT);
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ResTys.push_back(MVT::Other);
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SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
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if (!llvm::ModelWithRegSequence() || NumVecs < 2)
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if (NumVecs < 2)
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return VLd;
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SDValue RegSeq;
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@ -1156,7 +1135,6 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
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Chain = SDValue(VLd, 2 * NumVecs);
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// Combine the even and odd subregs to produce the result.
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if (llvm::ModelWithRegSequence()) {
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if (NumVecs == 1) {
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SDNode *Q = PairDRegs(VT, SDValue(VLd, 0), SDValue(VLd, 1));
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ReplaceUses(SDValue(N, 0), SDValue(Q, 0));
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@ -1169,12 +1147,6 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
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ReplaceUses(SDValue(N, 0), Q0);
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ReplaceUses(SDValue(N, 1), Q1);
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}
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} else {
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
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SDNode *Q = PairDRegs(VT, SDValue(VLd, 2*Vec), SDValue(VLd, 2*Vec+1));
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ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
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}
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}
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} else {
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// Otherwise, quad registers are loaded with two separate instructions,
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// where one loads the even registers and the other loads the odd registers.
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@ -1196,7 +1168,6 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
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SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 6);
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Chain = SDValue(VLdB, NumVecs+1);
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if (llvm::ModelWithRegSequence()) {
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SDValue V0 = SDValue(VLdA, 0);
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SDValue V1 = SDValue(VLdB, 0);
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SDValue V2 = SDValue(VLdA, 1);
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@ -1204,12 +1175,10 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
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SDValue V4 = SDValue(VLdA, 2);
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SDValue V5 = SDValue(VLdB, 2);
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SDValue V6 = (NumVecs == 3)
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? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT),
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0)
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? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 0)
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: SDValue(VLdA, 3);
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SDValue V7 = (NumVecs == 3)
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? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT),
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0)
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? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 0)
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: SDValue(VLdB, 3);
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SDValue RegSeq = SDValue(OctoDRegs(MVT::v8i64, V0, V1, V2, V3,
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V4, V5, V6, V7), 0);
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@ -1221,13 +1190,6 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
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dl, VT, RegSeq);
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ReplaceUses(SDValue(N, Vec), Q);
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}
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} else {
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// Combine the even and odd subregs to produce the result.
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
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SDNode *Q = PairDRegs(VT, SDValue(VLdA, Vec), SDValue(VLdB, Vec));
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ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
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}
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}
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}
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ReplaceUses(SDValue(N, NumVecs), Chain);
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return NULL;
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@ -1274,7 +1236,7 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
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Ops.push_back(Align);
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if (is64BitVector) {
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if (llvm::ModelWithRegSequence() && NumVecs >= 2) {
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if (NumVecs >= 2) {
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SDValue RegSeq;
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SDValue V0 = N->getOperand(0+3);
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SDValue V1 = N->getOperand(1+3);
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@ -1319,7 +1281,7 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
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// Quad registers are directly supported for VST1 and VST2,
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// storing pairs of D regs.
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unsigned Opc = QOpcodes0[OpcodeIndex];
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if (llvm::ModelWithRegSequence() && NumVecs == 2) {
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if (NumVecs == 2) {
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// First extract the pair of Q registers.
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SDValue Q0 = N->getOperand(3);
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SDValue Q1 = N->getOperand(4);
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@ -1357,7 +1319,7 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
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// Otherwise, quad registers are stored with two separate instructions,
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// where one stores the even registers and the other stores the odd registers.
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if (llvm::ModelWithRegSequence()) {
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// Form the QQQQ REG_SEQUENCE.
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SDValue V[8];
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for (unsigned Vec = 0, i = 0; Vec < NumVecs; ++Vec, i+=2) {
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@ -1399,34 +1361,6 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
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Chain = SDValue(VStB, 1);
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ReplaceUses(SDValue(N, 0), Chain);
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return NULL;
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} else {
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Ops.push_back(Reg0); // post-access address offset
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// Store the even subregs.
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT,
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N->getOperand(Vec+3)));
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Ops.push_back(Pred);
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Ops.push_back(Reg0); // predicate register
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Ops.push_back(Chain);
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unsigned Opc = QOpcodes0[OpcodeIndex];
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SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
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MVT::Other, Ops.data(), NumVecs+6);
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Chain = SDValue(VStA, 1);
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// Store the odd subregs.
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Ops[0] = SDValue(VStA, 0); // MemAddr
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
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Ops[Vec+3] = CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT,
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N->getOperand(Vec+3));
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Ops[NumVecs+5] = Chain;
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Opc = QOpcodes1[OpcodeIndex];
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SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
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MVT::Other, Ops.data(), NumVecs+6);
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Chain = SDValue(VStB, 1);
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ReplaceUses(SDValue(N, 0), Chain);
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return NULL;
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}
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}
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SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
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@ -1482,7 +1416,6 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
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unsigned Opc = 0;
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if (is64BitVector) {
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Opc = DOpcodes[OpcodeIndex];
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if (llvm::ModelWithRegSequence()) {
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SDValue RegSeq;
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SDValue V0 = N->getOperand(0+3);
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SDValue V1 = N->getOperand(1+3);
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@ -1497,20 +1430,12 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
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}
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// Now extract the D registers back out.
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT,
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RegSeq));
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT,
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RegSeq));
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, RegSeq));
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, RegSeq));
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if (NumVecs > 2)
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT,
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RegSeq));
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT,RegSeq));
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if (NumVecs > 3)
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT,
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RegSeq));
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} else {
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
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Ops.push_back(N->getOperand(Vec+3));
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}
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT,RegSeq));
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} else {
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// Check if this is loading the even or odd subreg of a Q register.
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if (Lane < NumElts) {
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@ -1520,7 +1445,6 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
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Opc = QOpcodes1[OpcodeIndex];
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}
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if (llvm::ModelWithRegSequence()) {
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SDValue RegSeq;
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SDValue V0 = N->getOperand(0+3);
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SDValue V1 = N->getOperand(1+3);
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@ -1539,12 +1463,6 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
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Ops.push_back(CurDAG->getTargetExtractSubreg(SubIdx+Vec*2, dl, RegVT,
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RegSeq));
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} else {
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// Extract the subregs of the input vector.
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
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Ops.push_back(CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
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N->getOperand(Vec+3)));
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}
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}
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Ops.push_back(getI32Imm(Lane));
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Ops.push_back(Pred);
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@ -1558,7 +1476,6 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
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ResTys.push_back(MVT::Other);
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SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(),NumVecs+6);
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if (llvm::ModelWithRegSequence()) {
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// Form a REG_SEQUENCE to force register allocation.
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SDValue RegSeq;
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if (is64BitVector) {
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@ -1610,24 +1527,6 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
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return NULL;
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}
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// For a 64-bit vector load to D registers, nothing more needs to be done.
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if (is64BitVector)
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return VLdLn;
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// For 128-bit vectors, take the 64-bit results of the load and insert them
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// as subregs into the result.
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
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SDValue QuadVec = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
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N->getOperand(Vec+3),
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SDValue(VLdLn, Vec));
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ReplaceUses(SDValue(N, Vec), QuadVec);
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}
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Chain = SDValue(VLdLn, NumVecs);
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ReplaceUses(SDValue(N, NumVecs), Chain);
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return NULL;
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}
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SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
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bool isSigned) {
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if (!Subtarget->hasV6T2Ops())
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@ -2410,9 +2309,3 @@ FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
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CodeGenOpt::Level OptLevel) {
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return new ARMDAGToDAGISel(TM, OptLevel);
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}
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/// ModelWithRegSequence - Return true if isel should use REG_SEQUENCE to model
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/// operations involving sub-registers.
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bool llvm::ModelWithRegSequence() {
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return UseRegSeq;
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}
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@ -109,10 +109,7 @@ void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
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}
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setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
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if (llvm::ModelWithRegSequence())
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setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
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else
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setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
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setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
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setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
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@ -467,8 +467,7 @@ bool NEONPreAllocPass::PreAllocNEONRegisters(MachineBasicBlock &MBB) {
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unsigned FirstOpnd, NumRegs, Offset, Stride;
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if (!isNEONMultiRegOp(MI->getOpcode(), FirstOpnd, NumRegs, Offset, Stride))
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continue;
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if (llvm::ModelWithRegSequence() &&
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FormsRegSequence(MI, FirstOpnd, NumRegs, Offset, Stride))
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if (FormsRegSequence(MI, FirstOpnd, NumRegs, Offset, Stride))
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continue;
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MachineBasicBlock::iterator NextI = llvm::next(MBBI);
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