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ARMCodeEmitter::emitMiscInstruction is dead. Long live

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ARMCodeEmitter::emitMiscInstruction!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116644 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
2010-10-15 23:35:12 +00:00
parent c9a91fdaf9
commit 07fda9f9b6
1 changed files with 1 additions and 45 deletions
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46
lib/Target/ARM/ARMCodeEmitter.cpp
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@@ -140,8 +140,6 @@ namespace {
void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
void emitMiscInstruction(const MachineInstr &MI);
void emitNEONLaneInstruction(const MachineInstr &MI); void emitNEONLaneInstruction(const MachineInstr &MI);
void emitNEONDupInstruction(const MachineInstr &MI); void emitNEONDupInstruction(const MachineInstr &MI);
void emitNEON1RegModImmInstruction(const MachineInstr &MI); void emitNEON1RegModImmInstruction(const MachineInstr &MI);
@@ -437,9 +435,7 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
case ARMII::VFPLdStMulFrm: case ARMII::VFPLdStMulFrm:
emitVFPLoadStoreMultipleInstruction(MI); emitVFPLoadStoreMultipleInstruction(MI);
break; break;
case ARMII::VFPMiscFrm:
emitMiscInstruction(MI);
break;
// NEON instructions. // NEON instructions.
case ARMII::NGetLnFrm: case ARMII::NGetLnFrm:
case ARMII::NSetLnFrm: case ARMII::NSetLnFrm:
@@ -1589,46 +1585,6 @@ ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
emitWordLE(Binary); emitWordLE(Binary);
} }
void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
unsigned Opcode = MI.getDesc().Opcode;
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
// Set the conditional execution predicate
Binary |= II->getPredicate(&MI) << ARMII::CondShift;
switch (Opcode) {
default:
llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
case ARM::FCONSTD:
case ARM::FCONSTS: {
// Encode Dd / Sd.
Binary |= encodeVFPRd(MI, 0);
// Encode imm., Table A7-18 VFP modified immediate constants
const MachineOperand &MO1 = MI.getOperand(1);
unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
.bitcastToAPInt().getHiBits(32).getLimitedValue());
unsigned ModifiedImm;
if(Opcode == ARM::FCONSTS)
ModifiedImm = (Imm & 0x80000000) >> 24 | // a
(Imm & 0x03F80000) >> 19; // bcdefgh
else // Opcode == ARM::FCONSTD
ModifiedImm = (Imm & 0x80000000) >> 24 | // a
(Imm & 0x007F0000) >> 16; // bcdefgh
// Insts{19-16} = abcd, Insts{3-0} = efgh
Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
Binary |= (ModifiedImm & 0xF);
break;
}
}
emitWordLE(Binary);
}
static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) { static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
unsigned RegD = MI.getOperand(OpIdx).getReg(); unsigned RegD = MI.getOperand(OpIdx).getReg();
unsigned Binary = 0; unsigned Binary = 0;