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Obsessive formatting changes. No functionality impact.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118103 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2010-11-02 22:53:11 +00:00
parent 0803ebe0c8
commit 0800ce7189
1 changed files with 38 additions and 32 deletions
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70
lib/Target/ARM/ARMMCCodeEmitter.cpp
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@ -132,9 +132,8 @@ public:
} // end anonymous namespace } // end anonymous namespace
MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
TargetMachine &TM, MCContext &Ctx) {
MCContext &Ctx) {
return new ARMMCCodeEmitter(TM, Ctx); return new ARMMCCodeEmitter(TM, Ctx);
} }
@ -143,29 +142,30 @@ MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &,
unsigned ARMMCCodeEmitter::getMachineOpValue(const MCInst &MI, unsigned ARMMCCodeEmitter::getMachineOpValue(const MCInst &MI,
const MCOperand &MO) const { const MCOperand &MO) const {
if (MO.isReg()) { if (MO.isReg()) {
unsigned regno = getARMRegisterNumbering(MO.getReg()); unsigned Reg = MO.getReg();
unsigned RegNo = getARMRegisterNumbering(Reg);
// Q registers are encodes as 2x their register number. // Q registers are encodes as 2x their register number.
switch (MO.getReg()) { switch (Reg) {
case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: default:
case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: return RegNo;
case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15: case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
return 2 * regno; case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
default: case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
return regno; return 2 * RegNo;
} }
} else if (MO.isImm()) { } else if (MO.isImm()) {
return static_cast<unsigned>(MO.getImm()); return static_cast<unsigned>(MO.getImm());
} else if (MO.isFPImm()) { } else if (MO.isFPImm()) {
return static_cast<unsigned>(APFloat(MO.getFPImm()) return static_cast<unsigned>(APFloat(MO.getFPImm())
.bitcastToAPInt().getHiBits(32).getLimitedValue()); .bitcastToAPInt().getHiBits(32).getLimitedValue());
} else {
#ifndef NDEBUG
errs() << MO;
#endif
llvm_unreachable(0);
} }
#ifndef NDEBUG
errs() << MO;
#endif
llvm_unreachable(0);
return 0; return 0;
} }
@ -206,15 +206,16 @@ uint32_t ARMMCCodeEmitter::getAddrModeImmOpValue(const MCInst &MI,
unsigned ARMMCCodeEmitter::getSORegOpValue(const MCInst &MI, unsigned ARMMCCodeEmitter::getSORegOpValue(const MCInst &MI,
unsigned OpIdx) const { unsigned OpIdx) const {
// Sub-operands are [reg, reg, imm]. The first register is Rm, the reg // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
// to be shifted. The second is either Rs, the amount to shift by, or // shifted. The second is either Rs, the amount to shift by, or reg0 in which
// reg0 in which case the imm contains the amount to shift by. // case the imm contains the amount to shift by.
//
// {3-0} = Rm. // {3-0} = Rm.
// {4} = 1 if reg shift, 0 if imm shift // {4} = 1 if reg shift, 0 if imm shift
// {6-5} = type // {6-5} = type
// If reg shift: // If reg shift:
// {7} = 0
// {11-8} = Rs // {11-8} = Rs
// {7} = 0
// else (imm shift) // else (imm shift)
// {11-7} = imm // {11-7} = imm
@ -258,6 +259,7 @@ unsigned ARMMCCodeEmitter::getSORegOpValue(const MCInst &MI,
case ARM_AM::ror: SBits = 0x6; break; case ARM_AM::ror: SBits = 0x6; break;
} }
} }
Binary |= SBits << 4; Binary |= SBits << 4;
if (SOpc == ARM_AM::rrx) if (SOpc == ARM_AM::rrx)
return Binary; return Binary;
@ -300,24 +302,28 @@ unsigned ARMMCCodeEmitter::getRegisterListOpValue(const MCInst &MI,
unsigned ARMMCCodeEmitter::getAddrMode6AddressOpValue(const MCInst &MI, unsigned ARMMCCodeEmitter::getAddrMode6AddressOpValue(const MCInst &MI,
unsigned Op) const { unsigned Op) const {
const MCOperand &Reg = MI.getOperand(Op); const MCOperand &Reg = MI.getOperand(Op);
const MCOperand &Imm = MI.getOperand(Op+1); const MCOperand &Imm = MI.getOperand(Op + 1);
unsigned RegNo = getARMRegisterNumbering(Reg.getReg()); unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
unsigned Align = Imm.getImm(); unsigned Align = 0;
switch(Align) {
case 2: case 4: case 8: Align = 0x01; break; switch (Imm.getImm()) {
case 16: Align = 0x02; break; default: break;
case 32: Align = 0x03; break; case 2:
default: Align = 0x00; break; case 4:
case 8: Align = 0x01; break;
case 16: Align = 0x02; break;
case 32: Align = 0x03; break;
} }
return RegNo | (Align << 4); return RegNo | (Align << 4);
} }
unsigned ARMMCCodeEmitter::getAddrMode6OffsetOpValue(const MCInst &MI, unsigned ARMMCCodeEmitter::getAddrMode6OffsetOpValue(const MCInst &MI,
unsigned Op) const { unsigned Op) const {
const MCOperand &regno = MI.getOperand(Op); const MCOperand &MO = MI.getOperand(Op);
if (regno.getReg() == 0) return 0x0D; if (MO.getReg() == 0) return 0x0D;
return regno.getReg(); return MO.getReg();
} }
void ARMMCCodeEmitter:: void ARMMCCodeEmitter::