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[AggressiveAntiDepBreaker] Use range loops for multimap access.
No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242620 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -509,15 +509,8 @@ BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
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// Check all references that need rewriting for Reg. For each, use
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// the corresponding register class to narrow the set of registers
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// that are appropriate for renaming.
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std::pair<std::multimap<unsigned,
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AggressiveAntiDepState::RegisterReference>::iterator,
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std::multimap<unsigned,
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AggressiveAntiDepState::RegisterReference>::iterator>
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Range = State->GetRegRefs().equal_range(Reg);
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for (std::multimap<unsigned,
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AggressiveAntiDepState::RegisterReference>::iterator Q = Range.first,
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QE = Range.second; Q != QE; ++Q) {
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const TargetRegisterClass *RC = Q->second.RC;
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for (const auto &Q : make_range(State->GetRegRefs().equal_range(Reg))) {
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const TargetRegisterClass *RC = Q.second.RC;
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if (!RC) continue;
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BitVector RCBV = TRI->getAllocatableSet(MF, RC);
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@ -685,9 +678,8 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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// We cannot rename 'Reg' to 'NewReg' if one of the uses of 'Reg' also
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// defines 'NewReg' via an early-clobber operand.
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auto Range = RegRefs.equal_range(Reg);
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for (auto Q = Range.first, QE = Range.second; Q != QE; ++Q) {
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auto UseMI = Q->second.Operand->getParent();
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for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
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MachineInstr *UseMI = Q.second.Operand->getParent();
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int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI);
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if (Idx == -1)
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continue;
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@ -920,23 +912,16 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
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// Update the references to the old register CurrReg to
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// refer to the new register NewReg.
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std::pair<std::multimap<unsigned,
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AggressiveAntiDepState::RegisterReference>::iterator,
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std::multimap<unsigned,
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AggressiveAntiDepState::RegisterReference>::iterator>
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Range = RegRefs.equal_range(CurrReg);
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for (std::multimap<unsigned,
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AggressiveAntiDepState::RegisterReference>::iterator
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Q = Range.first, QE = Range.second; Q != QE; ++Q) {
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Q->second.Operand->setReg(NewReg);
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for (const auto &Q : make_range(RegRefs.equal_range(CurrReg))) {
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Q.second.Operand->setReg(NewReg);
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// If the SU for the instruction being updated has debug
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// information related to the anti-dependency register, make
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// sure to update that as well.
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const SUnit *SU = MISUnitMap[Q->second.Operand->getParent()];
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const SUnit *SU = MISUnitMap[Q.second.Operand->getParent()];
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if (!SU) continue;
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for (DbgValueVector::iterator DVI = DbgValues.begin(),
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DVE = DbgValues.end(); DVI != DVE; ++DVI)
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if (DVI->second == Q->second.Operand->getParent())
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if (DVI->second == Q.second.Operand->getParent())
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UpdateDbgValue(DVI->first, AntiDepReg, NewReg);
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}
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