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Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -216,13 +216,14 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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// Check for explicit enable/disable of post-ra scheduling.
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TargetSubtarget::AntiDepBreakMode AntiDepMode = TargetSubtarget::ANTIDEP_NONE;
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TargetSubtarget::ExcludedRCVector ExcludedRCs;
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if (EnablePostRAScheduler.getPosition() > 0) {
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if (!EnablePostRAScheduler)
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return false;
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} else {
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// Check that post-RA scheduling is enabled for this target.
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const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>();
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if (!ST.enablePostRAScheduler(OptLevel, AntiDepMode))
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if (!ST.enablePostRAScheduler(OptLevel, AntiDepMode, ExcludedRCs))
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return false;
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}
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@@ -243,7 +244,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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(ScheduleHazardRecognizer *)new SimpleHazardRecognizer();
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AntiDepBreaker *ADB =
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((AntiDepMode == TargetSubtarget::ANTIDEP_ALL) ?
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(AntiDepBreaker *)new AggressiveAntiDepBreaker(Fn) :
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(AntiDepBreaker *)new AggressiveAntiDepBreaker(Fn, ExcludedRCs) :
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((AntiDepMode == TargetSubtarget::ANTIDEP_CRITICAL) ?
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(AntiDepBreaker *)new CriticalAntiDepBreaker(Fn) : NULL));
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