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[mips] Add definitions of micromips load and store instructions.

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Patch by Zoran Jovanovic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180241 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-04-25 01:21:25 +00:00
parent aa27161a01
commit 089741479b
4 changed files with 43 additions and 17 deletions
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12
lib/Target/Mips/MicroMipsInstrFormats.td
View File

@ -98,3 +98,15 @@ class SRLV_FM_MM<bits<10> funct, bit rotate> : MMArch {
let Inst{10} = rotate;
let Inst{9-0} = funct;
}
class LW_FM_MM<bits<6> op> : MMArch {
bits<5> rt;
bits<21> addr;
bits<32> Inst;
let Inst{31-26} = op;
let Inst{25-21} = rt;
let Inst{20-16} = addr{20-16};
let Inst{15-0} = addr{15-0};
}

10
lib/Target/Mips/MicroMipsInstrInfo.td
View File

@ -54,4 +54,14 @@ let isCodeGenOnly = 1 in {
SRA_FM_MM<0xc0, 0>;
def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", CPURegsOpnd>,
SRLV_FM_MM<0xd0, 0>;
/// Load and Store Instructions - aligned
defm LB_MM : LoadM<"lb", CPURegs, sextloadi8>, MMRel, LW_FM_MM<0x7>;
defm LBu_MM : LoadM<"lbu", CPURegs, zextloadi8>, MMRel, LW_FM_MM<0x5>;
defm LH_MM : LoadM<"lh", CPURegs, sextloadi16>, MMRel, LW_FM_MM<0xf>;
defm LHu_MM : LoadM<"lhu", CPURegs, zextloadi16>, MMRel, LW_FM_MM<0xd>;
defm LW_MM : LoadM<"lw", CPURegs>, MMRel, LW_FM_MM<0x3f>;
defm SB_MM : StoreM<"sb", CPURegs, truncstorei8>, MMRel, LW_FM_MM<0x6>;
defm SH_MM : StoreM<"sh", CPURegs, truncstorei16>, MMRel, LW_FM_MM<0xe>;
defm SW_MM : StoreM<"sw", CPURegs>, MMRel, LW_FM_MM<0x3e>;
}

2
lib/Target/Mips/MipsInstrFormats.td
View File

@ -549,7 +549,7 @@ class MFC1_FM<bits<5> funct> {
let Inst{10-0} = 0;
}
class LW_FM<bits<6> op> {
class LW_FM<bits<6> op> : StdArch {
bits<5> rt;
bits<21> addr;

36
lib/Target/Mips/MipsInstrInfo.td
View File

@ -440,18 +440,20 @@ class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
// Memory Load/Store
class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC,
Operand MemOpnd, ComplexPattern Addr> :
Operand MemOpnd, ComplexPattern Addr, string ofsuffix> :
InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
[(set RC:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI> {
[(set RC:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI,
!strconcat(opstr, ofsuffix)> {
let DecoderMethod = "DecodeMem";
let canFoldAsLoad = 1;
let mayLoad = 1;
}
class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
Operand MemOpnd, ComplexPattern Addr> :
Operand MemOpnd, ComplexPattern Addr, string ofsuffix> :
InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
[(OpNode RC:$rt, Addr:$addr)], NoItinerary, FrmI> {
[(OpNode RC:$rt, Addr:$addr)], NoItinerary, FrmI,
!strconcat(opstr, ofsuffix)> {
let DecoderMethod = "DecodeMem";
let mayStore = 1;
}
@ -459,8 +461,9 @@ class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
multiclass LoadM<string opstr, RegisterClass RC,
SDPatternOperator OpNode = null_frag,
ComplexPattern Addr = addr> {
def NAME : Load<opstr, OpNode, RC, mem, Addr>, Requires<[NotN64, HasStdEnc]>;
def _P8 : Load<opstr, OpNode, RC, mem64, Addr>,
def NAME : Load<opstr, OpNode, RC, mem, Addr, "">,
Requires<[NotN64, HasStdEnc]>;
def _P8 : Load<opstr, OpNode, RC, mem64, Addr, "_p8">,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
@ -470,8 +473,9 @@ multiclass LoadM<string opstr, RegisterClass RC,
multiclass StoreM<string opstr, RegisterClass RC,
SDPatternOperator OpNode = null_frag,
ComplexPattern Addr = addr> {
def NAME : Store<opstr, OpNode, RC, mem, Addr>, Requires<[NotN64, HasStdEnc]>;
def _P8 : Store<opstr, OpNode, RC, mem64, Addr>,
def NAME : Store<opstr, OpNode, RC, mem, Addr, "">,
Requires<[NotN64, HasStdEnc]>;
def _P8 : Store<opstr, OpNode, RC, mem64, Addr, "_p8">,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
@ -905,14 +909,14 @@ let Predicates = [HasMips32r2, HasStdEnc] in {
/// Load and Store Instructions
/// aligned
defm LB : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>;
defm LBu : LoadM<"lbu", CPURegs, zextloadi8, addrDefault>, LW_FM<0x24>;
defm LH : LoadM<"lh", CPURegs, sextloadi16, addrDefault>, LW_FM<0x21>;
defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>;
defm LW : LoadM<"lw", CPURegs, load, addrDefault>, LW_FM<0x23>;
defm SB : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>;
defm SH : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>;
defm SW : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>;
defm LB : LoadM<"lb", CPURegs, sextloadi8>, MMRel, LW_FM<0x20>;
defm LBu : LoadM<"lbu", CPURegs, zextloadi8, addrDefault>, MMRel, LW_FM<0x24>;
defm LH : LoadM<"lh", CPURegs, sextloadi16, addrDefault>, MMRel, LW_FM<0x21>;
defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, MMRel, LW_FM<0x25>;
defm LW : LoadM<"lw", CPURegs, load, addrDefault>, MMRel, LW_FM<0x23>;
defm SB : StoreM<"sb", CPURegs, truncstorei8>, MMRel, LW_FM<0x28>;
defm SH : StoreM<"sh", CPURegs, truncstorei16>, MMRel, LW_FM<0x29>;
defm SW : StoreM<"sw", CPURegs, store>, MMRel, LW_FM<0x2b>;
/// load/store left/right
defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>;