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When emiting a CopyFromReg and the source is already a vreg, do not bother

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creating a new vreg and inserting a copy: just use the input vreg directly.

This speeds up the compile (e.g. about 5% on mesa with a debug build of llc)
by not adding a bunch of copies and vregs to be coallesced away.  On mesa,
for example, this reduces the number of intervals from 168601 to 129040
going into the coallescer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23671 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-10-09 05:58:56 +00:00
parent 65a419a104
commit 089c25ccb3
1 changed files with 31 additions and 27 deletions
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58
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
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@ -1025,22 +1025,23 @@ void SimpleSched::EmitNode(NodeInfo *NI) {
} }
case ISD::CopyFromReg: { case ISD::CopyFromReg: {
unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
if (MRegisterInfo::isVirtualRegister(SrcReg)) {
VRBase = SrcReg; // Just use the input register directly!
break;
}
// Figure out the register class to create for the destreg. // Figure out the register class to create for the destreg.
const TargetRegisterClass *TRC = 0; const TargetRegisterClass *TRC = 0;
if (MRegisterInfo::isVirtualRegister(SrcReg)) {
TRC = RegMap->getRegClass(SrcReg); // Pick the register class of the right type that contains this physreg.
} else { for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
// Pick the register class of the right type that contains this physreg. E = MRI.regclass_end(); I != E; ++I)
for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(), if ((*I)->getType() == Node->getValueType(0) &&
E = MRI.regclass_end(); I != E; ++I) (*I)->contains(SrcReg)) {
if ((*I)->getType() == Node->getValueType(0) && TRC = *I;
(*I)->contains(SrcReg)) { break;
TRC = *I; }
break; assert(TRC && "Couldn't find register class for reg copy!");
}
assert(TRC && "Couldn't find register class for reg copy!");
}
// Create the reg, emit the copy. // Create the reg, emit the copy.
VRBase = RegMap->createVirtualRegister(TRC); VRBase = RegMap->createVirtualRegister(TRC);
@ -1206,21 +1207,24 @@ unsigned SimpleSched::EmitDAG(SDOperand Op) {
EmitDAG(Op.getOperand(0)); // Emit the chain. EmitDAG(Op.getOperand(0)); // Emit the chain.
unsigned SrcReg = cast<RegisterSDNode>(Op.getOperand(1))->getReg(); unsigned SrcReg = cast<RegisterSDNode>(Op.getOperand(1))->getReg();
// If the input is already a virtual register, just use it.
if (MRegisterInfo::isVirtualRegister(SrcReg)) {
ResultReg = SrcReg;
break;
}
// Figure out the register class to create for the destreg. // Figure out the register class to create for the destreg.
const TargetRegisterClass *TRC = 0; const TargetRegisterClass *TRC = 0;
if (MRegisterInfo::isVirtualRegister(SrcReg)) {
TRC = RegMap->getRegClass(SrcReg); // Pick the register class of the right type that contains this physreg.
} else { for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
// Pick the register class of the right type that contains this physreg. E = MRI.regclass_end(); I != E; ++I)
for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(), if ((*I)->getType() == Op.Val->getValueType(0) &&
E = MRI.regclass_end(); I != E; ++I) (*I)->contains(SrcReg)) {
if ((*I)->getType() == Op.Val->getValueType(0) && TRC = *I;
(*I)->contains(SrcReg)) { break;
TRC = *I; }
break; assert(TRC && "Couldn't find register class for reg copy!");
}
assert(TRC && "Couldn't find register class for reg copy!");
}
// Create the reg, emit the copy. // Create the reg, emit the copy.
ResultReg = RegMap->createVirtualRegister(TRC); ResultReg = RegMap->createVirtualRegister(TRC);