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Modify class ReadHardware and add definition of 64-bit version of instruction
RDHWR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146101 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -219,6 +219,8 @@ let Uses = [SP_64] in
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def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>,
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Requires<[IsN64]>;
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def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>;
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def DEXT : ExtBase<3, "dext", CPU64Regs>;
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def DINS : InsBase<7, "dins", CPU64Regs>;
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@ -614,8 +614,9 @@ class ByteSwap<bits<6> func, bits<5> sa, string instr_asm>:
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}
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// Read Hardware
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class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$rt), (ins HWRegs:$rd),
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"rdhwr\t$rt, $rd", [], IIAlu> {
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class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass>
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: FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd),
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"rdhwr\t$rt, $rd", [], IIAlu> {
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let rs = 0;
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let shamt = 0;
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}
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@ -901,7 +902,7 @@ def MSUBU : MArithR<5, "msubu", MipsMSubu>;
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def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
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Requires<[HasMips32]>;
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def RDHWR : ReadHardware;
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def RDHWR : ReadHardware<CPURegs, HWRegs>;
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def EXT : ExtBase<0, "ext", CPURegs>;
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def INS : InsBase<4, "ins", CPURegs>;
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