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Modify class ReadHardware and add definition of 64-bit version of instruction

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RDHWR. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146101 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-12-07 23:31:26 +00:00
parent f99c1e5a19
commit 08a7d92da6
2 changed files with 6 additions and 3 deletions
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2
lib/Target/Mips/Mips64InstrInfo.td
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@ -219,6 +219,8 @@ let Uses = [SP_64] in
def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>,
Requires<[IsN64]>;
def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>;
def DEXT : ExtBase<3, "dext", CPU64Regs>;
def DINS : InsBase<7, "dins", CPU64Regs>;

7
lib/Target/Mips/MipsInstrInfo.td
View File

@ -614,8 +614,9 @@ class ByteSwap<bits<6> func, bits<5> sa, string instr_asm>:
}
// Read Hardware
class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$rt), (ins HWRegs:$rd),
"rdhwr\t$rt, $rd", [], IIAlu> {
class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass>
: FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd),
"rdhwr\t$rt, $rd", [], IIAlu> {
let rs = 0;
let shamt = 0;
}
@ -901,7 +902,7 @@ def MSUBU : MArithR<5, "msubu", MipsMSubu>;
def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
Requires<[HasMips32]>;
def RDHWR : ReadHardware;
def RDHWR : ReadHardware<CPURegs, HWRegs>;
def EXT : ExtBase<0, "ext", CPURegs>;
def INS : InsBase<4, "ins", CPURegs>;