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Clang-format over X86AsmInstrumentation.*.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216536 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evgeniy Stepanov 2014-08-27 11:10:54 +00:00
parent e79a94a839
commit 08cb02e91a
2 changed files with 214 additions and 181 deletions
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377
lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
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@ -42,33 +42,35 @@ std::string FuncName(unsigned AccessSize, bool IsWrite) {
} }
class X86AddressSanitizer : public X86AsmInstrumentation { class X86AddressSanitizer : public X86AsmInstrumentation {
public: public:
X86AddressSanitizer(const MCSubtargetInfo &STI) X86AddressSanitizer(const MCSubtargetInfo &STI)
: X86AsmInstrumentation(STI), RepPrefix(false) {} : X86AsmInstrumentation(STI), RepPrefix(false) {}
virtual ~X86AddressSanitizer() {} virtual ~X86AddressSanitizer() {}
// X86AsmInstrumentation implementation: // X86AsmInstrumentation implementation:
virtual void InstrumentAndEmitInstruction( virtual void InstrumentAndEmitInstruction(const MCInst &Inst,
const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, OperandVector &Operands,
const MCInstrInfo &MII, MCStreamer &Out) override { MCContext &Ctx,
const MCInstrInfo &MII,
MCStreamer &Out) override {
InstrumentMOVS(Inst, Operands, Ctx, MII, Out); InstrumentMOVS(Inst, Operands, Ctx, MII, Out);
if (RepPrefix) if (RepPrefix) EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX));
EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX));
InstrumentMOV(Inst, Operands, Ctx, MII, Out); InstrumentMOV(Inst, Operands, Ctx, MII, Out);
RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX); RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX);
if (!RepPrefix) if (!RepPrefix) EmitInstruction(Out, Inst);
EmitInstruction(Out, Inst);
} }
// Should be implemented differently in x86_32 and x86_64 subclasses. // Should be implemented differently in x86_32 and x86_64 subclasses.
virtual void InstrumentMemOperandSmallImpl( virtual void InstrumentMemOperandSmallImpl(X86Operand &Op,
X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, unsigned AccessSize, bool IsWrite,
MCStreamer &Out) = 0; MCContext &Ctx,
virtual void InstrumentMemOperandLargeImpl( MCStreamer &Out) = 0;
X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, virtual void InstrumentMemOperandLargeImpl(X86Operand &Op,
MCStreamer &Out) = 0; unsigned AccessSize, bool IsWrite,
MCContext &Ctx,
MCStreamer &Out) = 0;
virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx, virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
MCStreamer &Out) = 0; MCStreamer &Out) = 0;
@ -83,14 +85,15 @@ public:
void EmitLabel(MCStreamer &Out, MCSymbol *Label) { Out.EmitLabel(Label); } void EmitLabel(MCStreamer &Out, MCSymbol *Label) { Out.EmitLabel(Label); }
protected: protected:
// True when previous instruction was actually REP prefix. // True when previous instruction was actually REP prefix.
bool RepPrefix; bool RepPrefix;
}; };
void X86AddressSanitizer::InstrumentMemOperand( void X86AddressSanitizer::InstrumentMemOperand(MCParsedAsmOperand &Op,
MCParsedAsmOperand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, unsigned AccessSize,
MCStreamer &Out) { bool IsWrite, MCContext &Ctx,
MCStreamer &Out) {
assert(Op.isMem() && "Op should be a memory operand."); assert(Op.isMem() && "Op should be a memory operand.");
assert((AccessSize & (AccessSize - 1)) == 0 && AccessSize <= 16 && assert((AccessSize & (AccessSize - 1)) == 0 && AccessSize <= 16 &&
"AccessSize should be a power of two, less or equal than 16."); "AccessSize should be a power of two, less or equal than 16.");
@ -107,9 +110,10 @@ void X86AddressSanitizer::InstrumentMemOperand(
InstrumentMemOperandLargeImpl(MemOp, AccessSize, IsWrite, Ctx, Out); InstrumentMemOperandLargeImpl(MemOp, AccessSize, IsWrite, Ctx, Out);
} }
void X86AddressSanitizer::InstrumentMOVSBase( void X86AddressSanitizer::InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg,
unsigned DstReg, unsigned SrcReg, unsigned CntReg, unsigned AccessSize, unsigned CntReg,
MCContext &Ctx, MCStreamer &Out) { unsigned AccessSize,
MCContext &Ctx, MCStreamer &Out) {
// FIXME: check whole ranges [DstReg .. DstReg + AccessSize * (CntReg - 1)] // FIXME: check whole ranges [DstReg .. DstReg + AccessSize * (CntReg - 1)]
// and [SrcReg .. SrcReg + AccessSize * (CntReg - 1)]. // and [SrcReg .. SrcReg + AccessSize * (CntReg - 1)].
@ -149,92 +153,95 @@ void X86AddressSanitizer::InstrumentMOVSBase(
} }
} }
void X86AddressSanitizer::InstrumentMOVS( void X86AddressSanitizer::InstrumentMOVS(const MCInst &Inst,
const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, OperandVector &Operands,
const MCInstrInfo &MII, MCStreamer &Out) { MCContext &Ctx, const MCInstrInfo &MII,
MCStreamer &Out) {
// Access size in bytes. // Access size in bytes.
unsigned AccessSize = 0; unsigned AccessSize = 0;
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case X86::MOVSB: case X86::MOVSB:
AccessSize = 1; AccessSize = 1;
break; break;
case X86::MOVSW: case X86::MOVSW:
AccessSize = 2; AccessSize = 2;
break; break;
case X86::MOVSL: case X86::MOVSL:
AccessSize = 4; AccessSize = 4;
break; break;
case X86::MOVSQ: case X86::MOVSQ:
AccessSize = 8; AccessSize = 8;
break; break;
default: default:
return; return;
} }
InstrumentMOVSImpl(AccessSize, Ctx, Out); InstrumentMOVSImpl(AccessSize, Ctx, Out);
} }
void X86AddressSanitizer::InstrumentMOV( void X86AddressSanitizer::InstrumentMOV(const MCInst &Inst,
const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, OperandVector &Operands, MCContext &Ctx,
const MCInstrInfo &MII, MCStreamer &Out) { const MCInstrInfo &MII,
MCStreamer &Out) {
// Access size in bytes. // Access size in bytes.
unsigned AccessSize = 0; unsigned AccessSize = 0;
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case X86::MOV8mi: case X86::MOV8mi:
case X86::MOV8mr: case X86::MOV8mr:
case X86::MOV8rm: case X86::MOV8rm:
AccessSize = 1; AccessSize = 1;
break; break;
case X86::MOV16mi: case X86::MOV16mi:
case X86::MOV16mr: case X86::MOV16mr:
case X86::MOV16rm: case X86::MOV16rm:
AccessSize = 2; AccessSize = 2;
break; break;
case X86::MOV32mi: case X86::MOV32mi:
case X86::MOV32mr: case X86::MOV32mr:
case X86::MOV32rm: case X86::MOV32rm:
AccessSize = 4; AccessSize = 4;
break; break;
case X86::MOV64mi32: case X86::MOV64mi32:
case X86::MOV64mr: case X86::MOV64mr:
case X86::MOV64rm: case X86::MOV64rm:
AccessSize = 8; AccessSize = 8;
break; break;
case X86::MOVAPDmr: case X86::MOVAPDmr:
case X86::MOVAPSmr: case X86::MOVAPSmr:
case X86::MOVAPDrm: case X86::MOVAPDrm:
case X86::MOVAPSrm: case X86::MOVAPSrm:
AccessSize = 16; AccessSize = 16;
break; break;
default: default:
return; return;
} }
const bool IsWrite = MII.get(Inst.getOpcode()).mayStore(); const bool IsWrite = MII.get(Inst.getOpcode()).mayStore();
for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) { for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
assert(Operands[Ix]); assert(Operands[Ix]);
MCParsedAsmOperand &Op = *Operands[Ix]; MCParsedAsmOperand &Op = *Operands[Ix];
if (Op.isMem()) if (Op.isMem()) InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out);
InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out);
} }
} }
class X86AddressSanitizer32 : public X86AddressSanitizer { class X86AddressSanitizer32 : public X86AddressSanitizer {
public: public:
static const long kShadowOffset = 0x20000000; static const long kShadowOffset = 0x20000000;
X86AddressSanitizer32(const MCSubtargetInfo &STI) X86AddressSanitizer32(const MCSubtargetInfo &STI)
: X86AddressSanitizer(STI) {} : X86AddressSanitizer(STI) {}
virtual ~X86AddressSanitizer32() {} virtual ~X86AddressSanitizer32() {}
virtual void InstrumentMemOperandSmallImpl( virtual void InstrumentMemOperandSmallImpl(X86Operand &Op,
X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, unsigned AccessSize, bool IsWrite,
MCStreamer &Out) override; MCContext &Ctx,
virtual void InstrumentMemOperandLargeImpl( MCStreamer &Out) override;
X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, virtual void InstrumentMemOperandLargeImpl(X86Operand &Op,
MCStreamer &Out) override; unsigned AccessSize, bool IsWrite,
MCContext &Ctx,
MCStreamer &Out) override;
virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx, virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
MCStreamer &Out) override; MCStreamer &Out) override;
@ -244,8 +251,10 @@ public:
EmitInstruction(Out, MCInstBuilder(X86::CLD)); EmitInstruction(Out, MCInstBuilder(X86::CLD));
EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS)); EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
EmitInstruction(Out, MCInstBuilder(X86::AND64ri8).addReg(X86::ESP) EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
.addReg(X86::ESP).addImm(-16)); .addReg(X86::ESP)
.addReg(X86::ESP)
.addImm(-16));
EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(AddressReg)); EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(AddressReg));
const std::string &Fn = FuncName(AccessSize, IsWrite); const std::string &Fn = FuncName(AccessSize, IsWrite);
@ -256,9 +265,11 @@ public:
} }
}; };
void X86AddressSanitizer32::InstrumentMemOperandSmallImpl( void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(X86Operand &Op,
X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, unsigned AccessSize,
MCStreamer &Out) { bool IsWrite,
MCContext &Ctx,
MCStreamer &Out) {
EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX)); EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX)); EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX));
EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EDX)); EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EDX));
@ -274,8 +285,9 @@ void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(
EmitInstruction( EmitInstruction(
Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX)); Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX));
EmitInstruction(Out, MCInstBuilder(X86::SHR32ri).addReg(X86::ECX) EmitInstruction(
.addReg(X86::ECX).addImm(3)); Out,
MCInstBuilder(X86::SHR32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(3));
{ {
MCInst Inst; MCInst Inst;
@ -296,31 +308,34 @@ void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(
EmitInstruction( EmitInstruction(
Out, MCInstBuilder(X86::MOV32rr).addReg(X86::EDX).addReg(X86::EAX)); Out, MCInstBuilder(X86::MOV32rr).addReg(X86::EDX).addReg(X86::EAX));
EmitInstruction(Out, MCInstBuilder(X86::AND32ri).addReg(X86::EDX) EmitInstruction(
.addReg(X86::EDX).addImm(7)); Out,
MCInstBuilder(X86::AND32ri).addReg(X86::EDX).addReg(X86::EDX).addImm(7));
switch (AccessSize) { switch (AccessSize) {
case 1: case 1:
break; break;
case 2: { case 2: {
MCInst Inst; MCInst Inst;
Inst.setOpcode(X86::LEA32r); Inst.setOpcode(X86::LEA32r);
Inst.addOperand(MCOperand::CreateReg(X86::EDX)); Inst.addOperand(MCOperand::CreateReg(X86::EDX));
const MCExpr *Disp = MCConstantExpr::Create(1, Ctx); const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
std::unique_ptr<X86Operand> Op( std::unique_ptr<X86Operand> Op(
X86Operand::CreateMem(0, Disp, X86::EDX, 0, 1, SMLoc(), SMLoc())); X86Operand::CreateMem(0, Disp, X86::EDX, 0, 1, SMLoc(), SMLoc()));
Op->addMemOperands(Inst, 5); Op->addMemOperands(Inst, 5);
EmitInstruction(Out, Inst); EmitInstruction(Out, Inst);
break; break;
} }
case 4: case 4:
EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8).addReg(X86::EDX) EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
.addReg(X86::EDX).addImm(3)); .addReg(X86::EDX)
break; .addReg(X86::EDX)
default: .addImm(3));
assert(false && "Incorrect access size"); break;
break; default:
assert(false && "Incorrect access size");
break;
} }
EmitInstruction( EmitInstruction(
@ -338,9 +353,11 @@ void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(
EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX)); EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
} }
void X86AddressSanitizer32::InstrumentMemOperandLargeImpl( void X86AddressSanitizer32::InstrumentMemOperandLargeImpl(X86Operand &Op,
X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, unsigned AccessSize,
MCStreamer &Out) { bool IsWrite,
MCContext &Ctx,
MCStreamer &Out) {
EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX)); EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX)); EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX));
EmitInstruction(Out, MCInstBuilder(X86::PUSHF32)); EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
@ -354,8 +371,9 @@ void X86AddressSanitizer32::InstrumentMemOperandLargeImpl(
} }
EmitInstruction( EmitInstruction(
Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX)); Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX));
EmitInstruction(Out, MCInstBuilder(X86::SHR32ri).addReg(X86::ECX) EmitInstruction(
.addReg(X86::ECX).addImm(3)); Out,
MCInstBuilder(X86::SHR32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(3));
{ {
MCInst Inst; MCInst Inst;
switch (AccessSize) { switch (AccessSize) {
@ -388,8 +406,9 @@ void X86AddressSanitizer32::InstrumentMemOperandLargeImpl(
EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX)); EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
} }
void X86AddressSanitizer32::InstrumentMOVSImpl( void X86AddressSanitizer32::InstrumentMOVSImpl(unsigned AccessSize,
unsigned AccessSize, MCContext &Ctx, MCStreamer &Out) { MCContext &Ctx,
MCStreamer &Out) {
EmitInstruction(Out, MCInstBuilder(X86::PUSHF32)); EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
// No need to test when ECX is equals to zero. // No need to test when ECX is equals to zero.
@ -408,23 +427,25 @@ void X86AddressSanitizer32::InstrumentMOVSImpl(
} }
class X86AddressSanitizer64 : public X86AddressSanitizer { class X86AddressSanitizer64 : public X86AddressSanitizer {
public: public:
static const long kShadowOffset = 0x7fff8000; static const long kShadowOffset = 0x7fff8000;
X86AddressSanitizer64(const MCSubtargetInfo &STI) X86AddressSanitizer64(const MCSubtargetInfo &STI)
: X86AddressSanitizer(STI) {} : X86AddressSanitizer(STI) {}
virtual ~X86AddressSanitizer64() {} virtual ~X86AddressSanitizer64() {}
virtual void InstrumentMemOperandSmallImpl( virtual void InstrumentMemOperandSmallImpl(X86Operand &Op,
X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, unsigned AccessSize, bool IsWrite,
MCStreamer &Out) override; MCContext &Ctx,
virtual void InstrumentMemOperandLargeImpl( MCStreamer &Out) override;
X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, virtual void InstrumentMemOperandLargeImpl(X86Operand &Op,
MCStreamer &Out) override; unsigned AccessSize, bool IsWrite,
MCContext &Ctx,
MCStreamer &Out) override;
virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx, virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
MCStreamer &Out) override; MCStreamer &Out) override;
private: private:
void EmitAdjustRSP(MCContext &Ctx, MCStreamer &Out, long Offset) { void EmitAdjustRSP(MCContext &Ctx, MCStreamer &Out, long Offset) {
MCInst Inst; MCInst Inst;
Inst.setOpcode(X86::LEA64r); Inst.setOpcode(X86::LEA64r);
@ -442,8 +463,10 @@ private:
EmitInstruction(Out, MCInstBuilder(X86::CLD)); EmitInstruction(Out, MCInstBuilder(X86::CLD));
EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS)); EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
EmitInstruction(Out, MCInstBuilder(X86::AND64ri8).addReg(X86::RSP) EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
.addReg(X86::RSP).addImm(-16)); .addReg(X86::RSP)
.addReg(X86::RSP)
.addImm(-16));
const std::string &Fn = FuncName(AccessSize, IsWrite); const std::string &Fn = FuncName(AccessSize, IsWrite);
MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn)); MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
@ -453,9 +476,11 @@ private:
} }
}; };
void X86AddressSanitizer64::InstrumentMemOperandSmallImpl( void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(X86Operand &Op,
X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, unsigned AccessSize,
MCStreamer &Out) { bool IsWrite,
MCContext &Ctx,
MCStreamer &Out) {
EmitAdjustRSP(Ctx, Out, -128); EmitAdjustRSP(Ctx, Out, -128);
EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX)); EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RCX)); EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RCX));
@ -470,8 +495,9 @@ void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(
} }
EmitInstruction( EmitInstruction(
Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RAX).addReg(X86::RDI)); Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RAX).addReg(X86::RDI));
EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX) EmitInstruction(
.addReg(X86::RAX).addImm(3)); Out,
MCInstBuilder(X86::SHR64ri).addReg(X86::RAX).addReg(X86::RAX).addImm(3));
{ {
MCInst Inst; MCInst Inst;
Inst.setOpcode(X86::MOV8rm); Inst.setOpcode(X86::MOV8rm);
@ -491,31 +517,34 @@ void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(
EmitInstruction( EmitInstruction(
Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EDI)); Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EDI));
EmitInstruction(Out, MCInstBuilder(X86::AND32ri).addReg(X86::ECX) EmitInstruction(
.addReg(X86::ECX).addImm(7)); Out,
MCInstBuilder(X86::AND32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(7));
switch (AccessSize) { switch (AccessSize) {
case 1: case 1:
break; break;
case 2: { case 2: {
MCInst Inst; MCInst Inst;
Inst.setOpcode(X86::LEA32r); Inst.setOpcode(X86::LEA32r);
Inst.addOperand(MCOperand::CreateReg(X86::ECX)); Inst.addOperand(MCOperand::CreateReg(X86::ECX));
const MCExpr *Disp = MCConstantExpr::Create(1, Ctx); const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
std::unique_ptr<X86Operand> Op( std::unique_ptr<X86Operand> Op(
X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc())); X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
Op->addMemOperands(Inst, 5); Op->addMemOperands(Inst, 5);
EmitInstruction(Out, Inst); EmitInstruction(Out, Inst);
break; break;
} }
case 4: case 4:
EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8).addReg(X86::ECX) EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
.addReg(X86::ECX).addImm(3)); .addReg(X86::ECX)
break; .addReg(X86::ECX)
default: .addImm(3));
assert(false && "Incorrect access size"); break;
break; default:
assert(false && "Incorrect access size");
break;
} }
EmitInstruction( EmitInstruction(
@ -534,9 +563,11 @@ void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(
EmitAdjustRSP(Ctx, Out, 128); EmitAdjustRSP(Ctx, Out, 128);
} }
void X86AddressSanitizer64::InstrumentMemOperandLargeImpl( void X86AddressSanitizer64::InstrumentMemOperandLargeImpl(X86Operand &Op,
X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, unsigned AccessSize,
MCStreamer &Out) { bool IsWrite,
MCContext &Ctx,
MCStreamer &Out) {
EmitAdjustRSP(Ctx, Out, -128); EmitAdjustRSP(Ctx, Out, -128);
EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX)); EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
EmitInstruction(Out, MCInstBuilder(X86::PUSHF64)); EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
@ -548,20 +579,21 @@ void X86AddressSanitizer64::InstrumentMemOperandLargeImpl(
Op.addMemOperands(Inst, 5); Op.addMemOperands(Inst, 5);
EmitInstruction(Out, Inst); EmitInstruction(Out, Inst);
} }
EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX) EmitInstruction(
.addReg(X86::RAX).addImm(3)); Out,
MCInstBuilder(X86::SHR64ri).addReg(X86::RAX).addReg(X86::RAX).addImm(3));
{ {
MCInst Inst; MCInst Inst;
switch (AccessSize) { switch (AccessSize) {
case 8: case 8:
Inst.setOpcode(X86::CMP8mi); Inst.setOpcode(X86::CMP8mi);
break; break;
case 16: case 16:
Inst.setOpcode(X86::CMP16mi); Inst.setOpcode(X86::CMP16mi);
break; break;
default: default:
assert(false && "Incorrect access size"); assert(false && "Incorrect access size");
break; break;
} }
const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx); const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
std::unique_ptr<X86Operand> Op( std::unique_ptr<X86Operand> Op(
@ -583,8 +615,9 @@ void X86AddressSanitizer64::InstrumentMemOperandLargeImpl(
EmitAdjustRSP(Ctx, Out, 128); EmitAdjustRSP(Ctx, Out, 128);
} }
void X86AddressSanitizer64::InstrumentMOVSImpl( void X86AddressSanitizer64::InstrumentMOVSImpl(unsigned AccessSize,
unsigned AccessSize, MCContext &Ctx, MCStreamer &Out) { MCContext &Ctx,
MCStreamer &Out) {
EmitInstruction(Out, MCInstBuilder(X86::PUSHF64)); EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
// No need to test when RCX is equals to zero. // No need to test when RCX is equals to zero.
@ -602,7 +635,7 @@ void X86AddressSanitizer64::InstrumentMOVSImpl(
EmitInstruction(Out, MCInstBuilder(X86::POPF64)); EmitInstruction(Out, MCInstBuilder(X86::POPF64));
} }
} // End anonymous namespace } // End anonymous namespace
X86AsmInstrumentation::X86AsmInstrumentation(const MCSubtargetInfo &STI) X86AsmInstrumentation::X86AsmInstrumentation(const MCSubtargetInfo &STI)
: STI(STI) {} : STI(STI) {}
@ -620,9 +653,9 @@ void X86AsmInstrumentation::EmitInstruction(MCStreamer &Out,
Out.EmitInstruction(Inst, STI); Out.EmitInstruction(Inst, STI);
} }
X86AsmInstrumentation * X86AsmInstrumentation *CreateX86AsmInstrumentation(
CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions, const MCTargetOptions &MCOptions, const MCContext &Ctx,
const MCContext &Ctx, const MCSubtargetInfo &STI) { const MCSubtargetInfo &STI) {
Triple T(STI.getTargetTriple()); Triple T(STI.getTargetTriple());
const bool hasCompilerRTSupport = T.isOSLinux(); const bool hasCompilerRTSupport = T.isOSLinux();
if (ClAsanInstrumentAssembly && hasCompilerRTSupport && if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
@ -635,4 +668,4 @@ CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
return new X86AsmInstrumentation(STI); return new X86AsmInstrumentation(STI);
} }
} // End llvm namespace } // End llvm namespace

18
lib/Target/X86/AsmParser/X86AsmInstrumentation.h
View File

@ -26,12 +26,12 @@ class MCTargetOptions;
class X86AsmInstrumentation; class X86AsmInstrumentation;
X86AsmInstrumentation * X86AsmInstrumentation *CreateX86AsmInstrumentation(
CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions, const MCTargetOptions &MCOptions, const MCContext &Ctx,
const MCContext &Ctx, const MCSubtargetInfo &STI); const MCSubtargetInfo &STI);
class X86AsmInstrumentation { class X86AsmInstrumentation {
public: public:
virtual ~X86AsmInstrumentation(); virtual ~X86AsmInstrumentation();
// Tries to instrument and emit instruction. // Tries to instrument and emit instruction.
@ -40,10 +40,10 @@ public:
SmallVectorImpl<std::unique_ptr<MCParsedAsmOperand>> &Operands, SmallVectorImpl<std::unique_ptr<MCParsedAsmOperand>> &Operands,
MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out); MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
protected: protected:
friend X86AsmInstrumentation * friend X86AsmInstrumentation *CreateX86AsmInstrumentation(
CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions, const MCTargetOptions &MCOptions, const MCContext &Ctx,
const MCContext &Ctx, const MCSubtargetInfo &STI); const MCSubtargetInfo &STI);
X86AsmInstrumentation(const MCSubtargetInfo &STI); X86AsmInstrumentation(const MCSubtargetInfo &STI);
@ -52,6 +52,6 @@ protected:
const MCSubtargetInfo &STI; const MCSubtargetInfo &STI;
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif