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ARM scheduler model: Swift has varying latencies, uops for simple ALU ops

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178842 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Arnold Schwaighofer
2013-04-05 04:42:00 +00:00
parent d4d7613af3
commit 08da486557
4 changed files with 57 additions and 5 deletions
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12
lib/Target/ARM/ARMBaseInstrInfo.cpp
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@@ -4123,3 +4123,15 @@ breakPartialRegDependency(MachineBasicBlock::iterator MI,
bool ARMBaseInstrInfo::hasNOP() const {
return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;
}
bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
unsigned ShOpVal = MI->getOperand(3).getImm();
unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
// Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
((ShImm == 1 || ShImm == 2) &&
ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))
return true;
return false;
}