From 08fef885eb39339a47e3be7f0842b1db33683003 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Fri, 9 Sep 2011 22:24:36 +0000 Subject: [PATCH] Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb2.td | 4 +++- .../ARM/Disassembler/ARMDisassembler.cpp | 18 ++++++++++++++++++ .../ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 7 ++++++- test/MC/ARM/basic-thumb2-instructions.s | 6 ++++++ test/MC/Disassembler/ARM/thumb2.txt | 7 ++++++- 5 files changed, 39 insertions(+), 3 deletions(-) diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 4aaa014784d..4b64085563d 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -1146,7 +1146,7 @@ class T2PCOneRegImm { + IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> { let Inst{31-27} = 0b11110; let Inst{25-24} = 0b10; // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE) @@ -1163,6 +1163,8 @@ def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd), let Inst{26} = addr{11}; let Inst{14-12} = addr{10-8}; let Inst{7-0} = addr{7-0}; + + let DecoderMethod = "DecodeT2Adr"; } let neverHasSideEffects = 1, isReMaterializable = 1 in diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 937c65edc72..0edb7a5d93e 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -299,6 +299,8 @@ static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); #include "ARMGenDisassemblerTables.inc" #include "ARMGenInstrInfo.inc" @@ -3762,3 +3764,19 @@ DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, return S; } + +static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { + unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); + unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); + if (sign1 != sign2) return MCDisassembler::Fail; + + unsigned Val = fieldFromInstruction32(Insn, 0, 8); + Val |= fieldFromInstruction32(Insn, 12, 3) << 8; + Val |= fieldFromInstruction32(Insn, 26, 1) << 11; + Val |= sign1 << 12; + Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); + + return MCDisassembler::Success; +} + diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp index 7efab18f4be..e65af677f80 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -662,7 +662,12 @@ getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, if (MO.isExpr()) return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, Fixups); - return MO.getImm(); + int32_t Val = MO.getImm(); + if (Val < 0) { + Val *= -1; + Val |= 0x1000; + } + return Val; } /// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index bb57bb7ad88..4c4938fde77 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -107,6 +107,12 @@ _func: @ FIXME: ADR @------------------------------------------------------------------------------ + subw r11, pc, #3270 + adr.w r11, #-826 + +@ CHECK: subw r11, pc, #3270 @ encoding: [0xaf,0xf6,0xc6,0x4b] +@ CHECK: adr.w r11, #-826 @ encoding: [0xaf,0xf2,0x3a,0x3b] + @------------------------------------------------------------------------------ @ AND (immediate) @------------------------------------------------------------------------------ diff --git a/test/MC/Disassembler/ARM/thumb2.txt b/test/MC/Disassembler/ARM/thumb2.txt index c38c44c33d2..806c44f2b17 100644 --- a/test/MC/Disassembler/ARM/thumb2.txt +++ b/test/MC/Disassembler/ARM/thumb2.txt @@ -88,8 +88,13 @@ #------------------------------------------------------------------------------ -# FIXME: ADR +# ADR #------------------------------------------------------------------------------ +# CHECK: subw r11, pc, #3270 +# CHECK: subw r11, pc, #826 + +0xaf 0xf6 0xc6 0x4b +0xaf 0xf2 0x3a 0x3b #------------------------------------------------------------------------------ # AND (immediate)