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[ARM64,C++11] Clean up the ARM64 LOH collection pass.
Range'ify a bunch of loops, mainly. As a result, we have a variety of objects via reference rather than by pointer, so propogate that through the various helper functions where it makes sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206337 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
d66d570796
commit
09256c5bb5
@ -173,7 +173,7 @@ struct ARM64CollectLOH : public MachineFunctionPass {
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initializeARM64CollectLOHPass(*PassRegistry::getPassRegistry());
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}
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "ARM64 Collect Linker Optimization Hint (LOH)";
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@ -230,15 +230,14 @@ INITIALIZE_PASS_END(ARM64CollectLOH, "arm64-collect-loh",
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/// \param nbRegs is used internally allocate some memory. It must be consistent
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/// with the way sets is used.
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static SetOfMachineInstr &getSet(BlockToSetOfInstrsPerColor &sets,
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const MachineBasicBlock *MBB, unsigned reg,
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const MachineBasicBlock &MBB, unsigned reg,
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unsigned nbRegs) {
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SetOfMachineInstr *result;
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BlockToSetOfInstrsPerColor::iterator it = sets.find(MBB);
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if (it != sets.end()) {
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BlockToSetOfInstrsPerColor::iterator it = sets.find(&MBB);
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if (it != sets.end())
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result = it->second;
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} else {
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result = sets[MBB] = new SetOfMachineInstr[nbRegs];
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}
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else
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result = sets[&MBB] = new SetOfMachineInstr[nbRegs];
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return result[reg];
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}
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@ -251,15 +250,15 @@ static SetOfMachineInstr &getSet(BlockToSetOfInstrsPerColor &sets,
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/// "sets[reg]".
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/// \pre set[reg] is valid.
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static SetOfMachineInstr &getUses(InstrToInstrs *sets, unsigned reg,
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const MachineInstr *MI) {
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return sets[reg][MI];
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const MachineInstr &MI) {
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return sets[reg][&MI];
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}
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/// Same as getUses but does not modify the input map: sets.
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/// \return NULL if the couple (reg, MI) is not in sets.
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static const SetOfMachineInstr *getUses(const InstrToInstrs *sets, unsigned reg,
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const MachineInstr *MI) {
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InstrToInstrs::const_iterator Res = sets[reg].find(MI);
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const MachineInstr &MI) {
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InstrToInstrs::const_iterator Res = sets[reg].find(&MI);
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if (Res != sets[reg].end())
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return &(Res->second);
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return NULL;
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@ -276,41 +275,36 @@ static const SetOfMachineInstr *getUses(const InstrToInstrs *sets, unsigned reg,
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/// definition. It also consider definitions of ADRP instructions as uses and
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/// ignore other uses. The ADRPMode is used to collect the information for LHO
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/// that involve ADRP operation only.
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static void initReachingDef(MachineFunction *MF,
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static void initReachingDef(MachineFunction &MF,
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InstrToInstrs *ColorOpToReachedUses,
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BlockToInstrPerColor &Gen, BlockToRegSet &Kill,
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BlockToSetOfInstrsPerColor &ReachableUses,
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const MapRegToId &RegToId,
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const MachineInstr *DummyOp, bool ADRPMode) {
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const TargetMachine &TM = MF->getTarget();
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *TRI = TM.getRegisterInfo();
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unsigned NbReg = RegToId.size();
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for (MachineFunction::const_iterator IMBB = MF->begin(), IMBBEnd = MF->end();
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IMBB != IMBBEnd; ++IMBB) {
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const MachineBasicBlock *MBB = &(*IMBB);
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const MachineInstr **&BBGen = Gen[MBB];
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for (MachineBasicBlock &MBB : MF) {
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const MachineInstr **&BBGen = Gen[&MBB];
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BBGen = new const MachineInstr *[NbReg];
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memset(BBGen, 0, sizeof(const MachineInstr *) * NbReg);
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BitVector &BBKillSet = Kill[MBB];
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BitVector &BBKillSet = Kill[&MBB];
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BBKillSet.resize(NbReg);
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for (MachineBasicBlock::const_iterator II = MBB->begin(), IEnd = MBB->end();
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II != IEnd; ++II) {
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bool IsADRP = II->getOpcode() == ARM64::ADRP;
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for (const MachineInstr &MI : MBB) {
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bool IsADRP = MI.getOpcode() == ARM64::ADRP;
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// Process uses first.
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if (IsADRP || !ADRPMode)
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for (MachineInstr::const_mop_iterator IO = II->operands_begin(),
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IOEnd = II->operands_end();
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IO != IOEnd; ++IO) {
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for (const MachineOperand &MO : MI.operands()) {
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// Treat ADRP def as use, as the goal of the analysis is to find
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// ADRP defs reached by other ADRP defs.
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if (!IO->isReg() || (!ADRPMode && !IO->isUse()) ||
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(ADRPMode && (!IsADRP || !IO->isDef())))
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if (!MO.isReg() || (!ADRPMode && !MO.isUse()) ||
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(ADRPMode && (!IsADRP || !MO.isDef())))
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continue;
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unsigned CurReg = IO->getReg();
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unsigned CurReg = MO.getReg();
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MapRegToId::const_iterator ItCurRegId = RegToId.find(CurReg);
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if (ItCurRegId == RegToId.end())
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continue;
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@ -318,20 +312,18 @@ static void initReachingDef(MachineFunction *MF,
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// if CurReg has not been defined, this use is reachable.
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if (!BBGen[CurReg] && !BBKillSet.test(CurReg))
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getSet(ReachableUses, MBB, CurReg, NbReg).insert(&(*II));
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getSet(ReachableUses, MBB, CurReg, NbReg).insert(&MI);
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// current basic block definition for this color, if any, is in Gen.
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if (BBGen[CurReg])
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getUses(ColorOpToReachedUses, CurReg, BBGen[CurReg]).insert(&(*II));
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getUses(ColorOpToReachedUses, CurReg, *BBGen[CurReg]).insert(&MI);
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}
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// Process clobbers.
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for (MachineInstr::const_mop_iterator IO = II->operands_begin(),
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IOEnd = II->operands_end();
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IO != IOEnd; ++IO) {
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if (!IO->isRegMask())
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isRegMask())
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continue;
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// Clobbers kill the related colors.
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const uint32_t *PreservedRegs = IO->getRegMask();
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const uint32_t *PreservedRegs = MO.getRegMask();
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// Set generated regs.
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for (const auto Entry : RegToId) {
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@ -342,19 +334,17 @@ static void initReachingDef(MachineFunction *MF,
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// Do not register clobbered definition for no ADRP.
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// This definition is not used anyway (otherwise register
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// allocation is wrong).
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BBGen[Reg] = ADRPMode ? II : NULL;
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BBGen[Reg] = ADRPMode ? &MI : NULL;
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BBKillSet.set(Reg);
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}
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}
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}
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// Process defs
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for (MachineInstr::const_mop_iterator IO = II->operands_begin(),
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IOEnd = II->operands_end();
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IO != IOEnd; ++IO) {
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if (!IO->isReg() || !IO->isDef())
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// Process register defs.
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isReg() || !MO.isDef())
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continue;
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unsigned CurReg = IO->getReg();
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unsigned CurReg = MO.getReg();
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MapRegToId::const_iterator ItCurRegId = RegToId.find(CurReg);
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if (ItCurRegId == RegToId.end())
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continue;
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@ -365,19 +355,19 @@ static void initReachingDef(MachineFunction *MF,
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"Sub-register of an "
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"involved register, not recorded as involved!");
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BBKillSet.set(ItRegId->second);
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BBGen[ItRegId->second] = &(*II);
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BBGen[ItRegId->second] = &MI;
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}
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BBGen[ItCurRegId->second] = &(*II);
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BBGen[ItCurRegId->second] = &MI;
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}
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}
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// If we restrict our analysis to basic block scope, conservatively add a
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// dummy
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// use for each generated value.
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if (!ADRPMode && DummyOp && !MBB->succ_empty())
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if (!ADRPMode && DummyOp && !MBB.succ_empty())
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for (unsigned CurReg = 0; CurReg < NbReg; ++CurReg)
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if (BBGen[CurReg])
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getUses(ColorOpToReachedUses, CurReg, BBGen[CurReg]).insert(DummyOp);
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getUses(ColorOpToReachedUses, CurReg, *BBGen[CurReg]).insert(DummyOp);
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}
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}
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@ -390,7 +380,7 @@ static void initReachingDef(MachineFunction *MF,
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/// op.reachedUses
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///
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/// Out[bb] = Gen[bb] U (In[bb] - Kill[bb])
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static void reachingDefAlgorithm(MachineFunction *MF,
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static void reachingDefAlgorithm(MachineFunction &MF,
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InstrToInstrs *ColorOpToReachedUses,
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BlockToSetOfInstrsPerColor &In,
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BlockToSetOfInstrsPerColor &Out,
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@ -400,10 +390,7 @@ static void reachingDefAlgorithm(MachineFunction *MF,
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bool HasChanged;
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do {
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HasChanged = false;
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for (MachineFunction::const_iterator IMBB = MF->begin(),
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IMBBEnd = MF->end();
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IMBB != IMBBEnd; ++IMBB) {
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const MachineBasicBlock *MBB = &(*IMBB);
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for (MachineBasicBlock &MBB : MF) {
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unsigned CurReg;
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for (CurReg = 0; CurReg < NbReg; ++CurReg) {
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SetOfMachineInstr &BBInSet = getSet(In, MBB, CurReg, NbReg);
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@ -412,24 +399,21 @@ static void reachingDefAlgorithm(MachineFunction *MF,
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SetOfMachineInstr &BBOutSet = getSet(Out, MBB, CurReg, NbReg);
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unsigned Size = BBOutSet.size();
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// In[bb][color] = U Out[bb.predecessors][color]
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for (MachineBasicBlock::const_pred_iterator
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PredMBB = MBB->pred_begin(),
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EndPredMBB = MBB->pred_end();
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PredMBB != EndPredMBB; ++PredMBB) {
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for (MachineBasicBlock *PredMBB : MBB.predecessors()) {
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SetOfMachineInstr &PredOutSet = getSet(Out, *PredMBB, CurReg, NbReg);
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BBInSet.insert(PredOutSet.begin(), PredOutSet.end());
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}
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// insert reachableUses[bb][color] in each in[bb][color] op.reachedses
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for (const MachineInstr *MI: BBInSet) {
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for (const MachineInstr *MI : BBInSet) {
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SetOfMachineInstr &OpReachedUses =
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getUses(ColorOpToReachedUses, CurReg, MI);
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getUses(ColorOpToReachedUses, CurReg, *MI);
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OpReachedUses.insert(BBReachableUses.begin(), BBReachableUses.end());
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}
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// Out[bb] = Gen[bb] U (In[bb] - Kill[bb])
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if (!Kill[MBB].test(CurReg))
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if (!Kill[&MBB].test(CurReg))
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BBOutSet.insert(BBInSet.begin(), BBInSet.end());
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if (Gen[MBB][CurReg])
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BBOutSet.insert(Gen[MBB][CurReg]);
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if (Gen[&MBB][CurReg])
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BBOutSet.insert(Gen[&MBB][CurReg]);
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HasChanged |= BBOutSet.size() != Size;
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}
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}
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@ -442,21 +426,14 @@ static void finitReachingDef(BlockToSetOfInstrsPerColor &In,
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BlockToSetOfInstrsPerColor &Out,
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BlockToInstrPerColor &Gen,
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BlockToSetOfInstrsPerColor &ReachableUses) {
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for (BlockToSetOfInstrsPerColor::const_iterator IT = Out.begin(),
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End = Out.end();
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IT != End; ++IT)
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delete[] IT->second;
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for (BlockToSetOfInstrsPerColor::const_iterator IT = In.begin(),
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End = In.end();
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IT != End; ++IT)
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delete[] IT->second;
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for (BlockToSetOfInstrsPerColor::const_iterator IT = ReachableUses.begin(),
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End = ReachableUses.end();
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IT != End; ++IT)
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delete[] IT->second;
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for (BlockToInstrPerColor::const_iterator IT = Gen.begin(), End = Gen.end();
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IT != End; ++IT)
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delete[] IT->second;
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for (auto &IT : Out)
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delete[] IT.second;
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for (auto &IT : In)
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delete[] IT.second;
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for (auto &IT : ReachableUses)
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delete[] IT.second;
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for (auto &IT : Gen)
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delete[] IT.second;
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}
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/// Reaching definition algorithm.
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@ -470,7 +447,7 @@ static void finitReachingDef(BlockToSetOfInstrsPerColor &In,
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/// @p DummyOp.
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/// \pre ColorOpToReachedUses is an array of at least number of registers of
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/// InstrToInstrs.
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static void reachingDef(MachineFunction *MF,
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static void reachingDef(MachineFunction &MF,
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InstrToInstrs *ColorOpToReachedUses,
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const MapRegToId &RegToId, bool ADRPMode = false,
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const MachineInstr *DummyOp = NULL) {
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@ -511,18 +488,12 @@ static void printReachingDef(const InstrToInstrs *ColorOpToReachedUses,
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continue;
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DEBUG(dbgs() << "*** Reg " << PrintReg(IdToReg[CurReg], TRI) << " ***\n");
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InstrToInstrs::const_iterator DefsIt = ColorOpToReachedUses[CurReg].begin();
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InstrToInstrs::const_iterator DefsItEnd =
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ColorOpToReachedUses[CurReg].end();
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for (; DefsIt != DefsItEnd; ++DefsIt) {
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for (const auto &DefsIt : ColorOpToReachedUses[CurReg]) {
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DEBUG(dbgs() << "Def:\n");
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DEBUG(DefsIt->first->print(dbgs()));
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DEBUG(DefsIt.first->print(dbgs()));
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DEBUG(dbgs() << "Reachable uses:\n");
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for (SetOfMachineInstr::const_iterator UsesIt = DefsIt->second.begin(),
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UsesItEnd = DefsIt->second.end();
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UsesIt != UsesItEnd; ++UsesIt) {
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DEBUG((*UsesIt)->print(dbgs()));
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}
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for (const MachineInstr *MI : DefsIt.second)
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DEBUG(MI->print(dbgs()));
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}
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}
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}
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@ -603,34 +574,29 @@ static void reachedUsesToDefs(InstrToInstrs &UseToReachingDefs,
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if (ColorOpToReachedUses[CurReg].empty())
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continue;
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InstrToInstrs::const_iterator DefsIt = ColorOpToReachedUses[CurReg].begin();
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InstrToInstrs::const_iterator DefsItEnd =
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ColorOpToReachedUses[CurReg].end();
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for (; DefsIt != DefsItEnd; ++DefsIt) {
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for (SetOfMachineInstr::const_iterator UsesIt = DefsIt->second.begin(),
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UsesItEnd = DefsIt->second.end();
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UsesIt != UsesItEnd; ++UsesIt) {
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const MachineInstr *Def = DefsIt->first;
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for (const auto &DefsIt : ColorOpToReachedUses[CurReg]) {
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for (const MachineInstr *MI : DefsIt.second) {
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const MachineInstr *Def = DefsIt.first;
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MapRegToId::const_iterator It;
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// if all the reaching defs are not adrp, this use will not be
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// simplifiable.
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if ((ADRPMode && Def->getOpcode() != ARM64::ADRP) ||
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(!ADRPMode && !canDefBePartOfLOH(Def)) ||
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(!ADRPMode && isCandidateStore(*UsesIt) &&
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(!ADRPMode && isCandidateStore(MI) &&
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// store are LOH candidate iff the end of the chain is used as
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// base.
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((It = RegToId.find((*UsesIt)->getOperand(1).getReg())) == EndIt ||
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((It = RegToId.find((MI)->getOperand(1).getReg())) == EndIt ||
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It->second != CurReg))) {
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NotCandidate.insert(*UsesIt);
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NotCandidate.insert(MI);
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continue;
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}
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// Do not consider self reaching as a simplifiable case for ADRP.
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if (!ADRPMode || *UsesIt != DefsIt->first) {
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UseToReachingDefs[*UsesIt].insert(DefsIt->first);
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if (!ADRPMode || MI != DefsIt.first) {
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UseToReachingDefs[MI].insert(DefsIt.first);
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// If UsesIt has several reaching definitions, it is not
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// candidate for simplificaton in non-ADRPMode.
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if (!ADRPMode && UseToReachingDefs[*UsesIt].size() > 1)
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NotCandidate.insert(*UsesIt);
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if (!ADRPMode && UseToReachingDefs[MI].size() > 1)
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NotCandidate.insert(MI);
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}
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}
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}
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@ -747,8 +713,9 @@ static bool isCandidate(const MachineInstr *Instr,
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if (!MDT->dominates(Def, Instr))
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return false;
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// Move one node up in the simple chain.
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if (UseToDefs.find(Def) == UseToDefs.end()
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// The map may contain garbage we have to ignore.
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if (UseToDefs.find(Def) ==
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UseToDefs.end()
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// The map may contain garbage we have to ignore.
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||
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UseToDefs.find(Def)->second.empty())
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return false;
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@ -764,7 +731,7 @@ static bool isCandidate(const MachineInstr *Instr,
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return false;
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}
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static bool registerADRCandidate(const MachineInstr *Use,
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static bool registerADRCandidate(const MachineInstr &Use,
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const InstrToInstrs &UseToDefs,
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const InstrToInstrs *DefsPerColorToUses,
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ARM64FunctionInfo &ARM64FI,
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@ -773,38 +740,38 @@ static bool registerADRCandidate(const MachineInstr *Use,
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// Look for opportunities to turn ADRP -> ADD or
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// ADRP -> LDR GOTPAGEOFF into ADR.
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// If ADRP has more than one use. Give up.
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if (Use->getOpcode() != ARM64::ADDXri &&
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(Use->getOpcode() != ARM64::LDRXui ||
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!(Use->getOperand(2).getTargetFlags() & ARM64II::MO_GOT)))
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if (Use.getOpcode() != ARM64::ADDXri &&
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(Use.getOpcode() != ARM64::LDRXui ||
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!(Use.getOperand(2).getTargetFlags() & ARM64II::MO_GOT)))
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return false;
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InstrToInstrs::const_iterator It = UseToDefs.find(Use);
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InstrToInstrs::const_iterator It = UseToDefs.find(&Use);
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// The map may contain garbage that we need to ignore.
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if (It == UseToDefs.end() || It->second.empty())
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return false;
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const MachineInstr *Def = *It->second.begin();
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if (Def->getOpcode() != ARM64::ADRP)
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const MachineInstr &Def = **It->second.begin();
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if (Def.getOpcode() != ARM64::ADRP)
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return false;
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// Check the number of users of ADRP.
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const SetOfMachineInstr *Users =
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getUses(DefsPerColorToUses,
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RegToId.find(Def->getOperand(0).getReg())->second, Def);
|
||||
RegToId.find(Def.getOperand(0).getReg())->second, Def);
|
||||
if (Users->size() > 1) {
|
||||
++NumADRComplexCandidate;
|
||||
return false;
|
||||
}
|
||||
++NumADRSimpleCandidate;
|
||||
assert((!InvolvedInLOHs || InvolvedInLOHs->insert(Def)) &&
|
||||
assert((!InvolvedInLOHs || InvolvedInLOHs->insert(&Def)) &&
|
||||
"ADRP already involved in LOH.");
|
||||
assert((!InvolvedInLOHs || InvolvedInLOHs->insert(Use)) &&
|
||||
assert((!InvolvedInLOHs || InvolvedInLOHs->insert(&Use)) &&
|
||||
"ADD already involved in LOH.");
|
||||
DEBUG(dbgs() << "Record AdrpAdd\n" << *Def << '\n' << *Use << '\n');
|
||||
DEBUG(dbgs() << "Record AdrpAdd\n" << Def << '\n' << Use << '\n');
|
||||
|
||||
SmallVector<const MachineInstr *, 2> Args;
|
||||
Args.push_back(Def);
|
||||
Args.push_back(Use);
|
||||
Args.push_back(&Def);
|
||||
Args.push_back(&Use);
|
||||
|
||||
ARM64FI.addLOHDirective(Use->getOpcode() == ARM64::ADDXri ? MCLOH_AdrpAdd
|
||||
: MCLOH_AdrpLdrGot,
|
||||
ARM64FI.addLOHDirective(Use.getOpcode() == ARM64::ADDXri ? MCLOH_AdrpAdd
|
||||
: MCLOH_AdrpLdrGot,
|
||||
Args);
|
||||
return true;
|
||||
}
|
||||
@ -831,20 +798,18 @@ static void computeOthers(const InstrToInstrs &UseToDefs,
|
||||
// to be changed.
|
||||
SetOfMachineInstr PotentialCandidates;
|
||||
SetOfMachineInstr PotentialADROpportunities;
|
||||
for (InstrToInstrs::const_iterator UseIt = UseToDefs.begin(),
|
||||
EndUseIt = UseToDefs.end();
|
||||
UseIt != EndUseIt; ++UseIt) {
|
||||
for (auto &Use : UseToDefs) {
|
||||
// If no definition is available, this is a non candidate.
|
||||
if (UseIt->second.empty())
|
||||
if (Use.second.empty())
|
||||
continue;
|
||||
// Keep only instructions that are load or store and at the end of
|
||||
// a ADRP -> ADD/LDR/Nothing chain.
|
||||
// We already filtered out the no-chain cases.
|
||||
if (!isCandidate(UseIt->first, UseToDefs, MDT)) {
|
||||
PotentialADROpportunities.insert(UseIt->first);
|
||||
if (!isCandidate(Use.first, UseToDefs, MDT)) {
|
||||
PotentialADROpportunities.insert(Use.first);
|
||||
continue;
|
||||
}
|
||||
PotentialCandidates.insert(UseIt->first);
|
||||
PotentialCandidates.insert(Use.first);
|
||||
}
|
||||
|
||||
// Make the following distinctions for statistics as the linker does
|
||||
@ -866,10 +831,7 @@ static void computeOthers(const InstrToInstrs &UseToDefs,
|
||||
#ifdef DEBUG
|
||||
SetOfMachineInstr DefsOfPotentialCandidates;
|
||||
#endif
|
||||
for (CandidateIt = PotentialCandidates.begin(),
|
||||
EndCandidateIt = PotentialCandidates.end();
|
||||
CandidateIt != EndCandidateIt; ++CandidateIt) {
|
||||
const MachineInstr *Candidate = *CandidateIt;
|
||||
for (const MachineInstr *Candidate : PotentialCandidates) {
|
||||
// Get the definition of the candidate i.e., ADD or LDR.
|
||||
const MachineInstr *Def = *UseToDefs.find(Candidate)->second.begin();
|
||||
// Record the elements of the chain.
|
||||
@ -880,20 +842,20 @@ static void computeOthers(const InstrToInstrs &UseToDefs,
|
||||
// Check the number of users of this node.
|
||||
const SetOfMachineInstr *Users =
|
||||
getUses(DefsPerColorToUses,
|
||||
RegToId.find(Def->getOperand(0).getReg())->second, Def);
|
||||
RegToId.find(Def->getOperand(0).getReg())->second, *Def);
|
||||
if (Users->size() > 1) {
|
||||
#ifdef DEBUG
|
||||
// if all the uses of this def are in potential candidate, this is
|
||||
// a complex candidate of level 2.
|
||||
SetOfMachineInstr::const_iterator UseIt = Users->begin();
|
||||
SetOfMachineInstr::const_iterator EndUseIt = Users->end();
|
||||
for (; UseIt != EndUseIt; ++UseIt) {
|
||||
if (!PotentialCandidates.count(*UseIt)) {
|
||||
bool IsLevel2 = true;
|
||||
for (const MachineInstr *MI : *Users) {
|
||||
if (!PotentialCandidates.count(MI)) {
|
||||
++NumTooCplxLvl2;
|
||||
IsLevel2 = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (UseIt == EndUseIt)
|
||||
if (IsLevel2)
|
||||
++NumCplxLvl2;
|
||||
#endif // DEBUG
|
||||
PotentialADROpportunities.insert(Def);
|
||||
@ -908,7 +870,7 @@ static void computeOthers(const InstrToInstrs &UseToDefs,
|
||||
// Check the number of users of the first node in the chain, i.e., ADRP
|
||||
const SetOfMachineInstr *Users =
|
||||
getUses(DefsPerColorToUses,
|
||||
RegToId.find(Def->getOperand(0).getReg())->second, Def);
|
||||
RegToId.find(Def->getOperand(0).getReg())->second, *Def);
|
||||
if (Users->size() > 1) {
|
||||
#ifdef DEBUG
|
||||
// if all the uses of this def are in the defs of the potential candidate,
|
||||
@ -1030,8 +992,8 @@ static void computeOthers(const InstrToInstrs &UseToDefs,
|
||||
}
|
||||
|
||||
// Now, we grabbed all the big patterns, check ADR opportunities.
|
||||
for (const MachineInstr *Candidate: PotentialADROpportunities)
|
||||
registerADRCandidate(Candidate, UseToDefs, DefsPerColorToUses, ARM64FI,
|
||||
for (const MachineInstr *Candidate : PotentialADROpportunities)
|
||||
registerADRCandidate(*Candidate, UseToDefs, DefsPerColorToUses, ARM64FI,
|
||||
InvolvedInLOHs, RegToId);
|
||||
}
|
||||
|
||||
@ -1053,18 +1015,14 @@ static void collectInvolvedReg(MachineFunction &MF, MapRegToId &RegToId,
|
||||
}
|
||||
|
||||
DEBUG(dbgs() << "** Collect Involved Register\n");
|
||||
for (MachineFunction::const_iterator IMBB = MF.begin(), IMBBEnd = MF.end();
|
||||
IMBB != IMBBEnd; ++IMBB)
|
||||
for (MachineBasicBlock::const_iterator II = IMBB->begin(),
|
||||
IEnd = IMBB->end();
|
||||
II != IEnd; ++II) {
|
||||
|
||||
if (!canDefBePartOfLOH(II))
|
||||
for (const auto &MBB : MF) {
|
||||
for (const MachineInstr &MI : MBB) {
|
||||
if (!canDefBePartOfLOH(&MI))
|
||||
continue;
|
||||
|
||||
// Process defs
|
||||
for (MachineInstr::const_mop_iterator IO = II->operands_begin(),
|
||||
IOEnd = II->operands_end();
|
||||
for (MachineInstr::const_mop_iterator IO = MI.operands_begin(),
|
||||
IOEnd = MI.operands_end();
|
||||
IO != IOEnd; ++IO) {
|
||||
if (!IO->isReg() || !IO->isDef())
|
||||
continue;
|
||||
@ -1079,21 +1037,22 @@ static void collectInvolvedReg(MachineFunction &MF, MapRegToId &RegToId,
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool ARM64CollectLOH::runOnMachineFunction(MachineFunction &Fn) {
|
||||
const TargetMachine &TM = Fn.getTarget();
|
||||
bool ARM64CollectLOH::runOnMachineFunction(MachineFunction &MF) {
|
||||
const TargetMachine &TM = MF.getTarget();
|
||||
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
|
||||
const MachineDominatorTree *MDT = &getAnalysis<MachineDominatorTree>();
|
||||
|
||||
MapRegToId RegToId;
|
||||
MapIdToReg IdToReg;
|
||||
ARM64FunctionInfo *ARM64FI = Fn.getInfo<ARM64FunctionInfo>();
|
||||
ARM64FunctionInfo *ARM64FI = MF.getInfo<ARM64FunctionInfo>();
|
||||
assert(ARM64FI && "No MachineFunctionInfo for this function!");
|
||||
|
||||
DEBUG(dbgs() << "Looking for LOH in " << Fn.getName() << '\n');
|
||||
DEBUG(dbgs() << "Looking for LOH in " << MF.getName() << '\n');
|
||||
|
||||
collectInvolvedReg(Fn, RegToId, IdToReg, TRI);
|
||||
collectInvolvedReg(MF, RegToId, IdToReg, TRI);
|
||||
if (RegToId.empty())
|
||||
return false;
|
||||
|
||||
@ -1103,7 +1062,7 @@ bool ARM64CollectLOH::runOnMachineFunction(MachineFunction &Fn) {
|
||||
static_cast<const ARM64InstrInfo *>(TM.getInstrInfo());
|
||||
// For local analysis, create a dummy operation to record uses that are not
|
||||
// local.
|
||||
DummyOp = Fn.CreateMachineInstr(TII->get(ARM64::COPY), DebugLoc());
|
||||
DummyOp = MF.CreateMachineInstr(TII->get(ARM64::COPY), DebugLoc());
|
||||
}
|
||||
|
||||
unsigned NbReg = RegToId.size();
|
||||
@ -1114,7 +1073,7 @@ bool ARM64CollectLOH::runOnMachineFunction(MachineFunction &Fn) {
|
||||
|
||||
// Compute the reaching def in ADRP mode, meaning ADRP definitions
|
||||
// are first considered as uses.
|
||||
reachingDef(&Fn, ColorOpToReachedUses, RegToId, true, DummyOp);
|
||||
reachingDef(MF, ColorOpToReachedUses, RegToId, true, DummyOp);
|
||||
DEBUG(dbgs() << "ADRP reaching defs\n");
|
||||
DEBUG(printReachingDef(ColorOpToReachedUses, NbReg, TRI, IdToReg));
|
||||
|
||||
@ -1131,7 +1090,7 @@ bool ARM64CollectLOH::runOnMachineFunction(MachineFunction &Fn) {
|
||||
ColorOpToReachedUses = new InstrToInstrs[NbReg];
|
||||
|
||||
// first perform a regular reaching def analysis.
|
||||
reachingDef(&Fn, ColorOpToReachedUses, RegToId, false, DummyOp);
|
||||
reachingDef(MF, ColorOpToReachedUses, RegToId, false, DummyOp);
|
||||
DEBUG(dbgs() << "All reaching defs\n");
|
||||
DEBUG(printReachingDef(ColorOpToReachedUses, NbReg, TRI, IdToReg));
|
||||
|
||||
@ -1145,7 +1104,7 @@ bool ARM64CollectLOH::runOnMachineFunction(MachineFunction &Fn) {
|
||||
delete[] ColorOpToReachedUses;
|
||||
|
||||
if (BasicBlockScopeOnly)
|
||||
Fn.DeleteMachineInstr(DummyOp);
|
||||
MF.DeleteMachineInstr(DummyOp);
|
||||
|
||||
return Modified;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user