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The new LDR* instruction patterns should handle the necessary encoding of

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operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117461 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-10-27 17:52:51 +00:00
parent 633919c79a
commit 093177d5cd
1 changed files with 7 additions and 0 deletions
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7
lib/Target/ARM/ARMCodeEmitter.cpp
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@ -946,6 +946,13 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
// If this is an LDRi12, LDRrs, or LDRcp, nothing more needs be done.
if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRrs
|| MI.getOpcode() == ARM::LDRcp) {
emitWordLE(Binary);
return;
}
// Set the conditional execution predicate
Binary |= II->getPredicate(&MI) << ARMII::CondShift;