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https://github.com/c64scene-ar/llvm-6502.git
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[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206254 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -631,7 +631,7 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
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for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
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Record *PRDef = ProcModel.ProcResourceDefs[i];
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Record *SuperDef = 0;
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Record *SuperDef = nullptr;
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unsigned SuperIdx = 0;
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unsigned NumUnits = 0;
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int BufferSize = PRDef->getValueAsInt("BufferSize");
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@@ -676,7 +676,7 @@ Record *SubtargetEmitter::FindWriteResources(
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if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes"))
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return SchedWrite.TheDef;
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Record *AliasDef = 0;
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Record *AliasDef = nullptr;
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for (RecIter AI = SchedWrite.Aliases.begin(), AE = SchedWrite.Aliases.end();
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AI != AE; ++AI) {
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const CodeGenSchedRW &AliasRW =
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@@ -696,7 +696,7 @@ Record *SubtargetEmitter::FindWriteResources(
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return AliasDef;
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// Check this processor's list of write resources.
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Record *ResDef = 0;
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Record *ResDef = nullptr;
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for (RecIter WRI = ProcModel.WriteResDefs.begin(),
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WRE = ProcModel.WriteResDefs.end(); WRI != WRE; ++WRI) {
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if (!(*WRI)->isSubClassOf("WriteRes"))
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@@ -730,7 +730,7 @@ Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
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return SchedRead.TheDef;
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// Check this processor's list of aliases for SchedRead.
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Record *AliasDef = 0;
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Record *AliasDef = nullptr;
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for (RecIter AI = SchedRead.Aliases.begin(), AE = SchedRead.Aliases.end();
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AI != AE; ++AI) {
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const CodeGenSchedRW &AliasRW =
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@@ -750,7 +750,7 @@ Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
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return AliasDef;
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// Check this processor's ReadAdvanceList.
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Record *ResDef = 0;
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Record *ResDef = nullptr;
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for (RecIter RAI = ProcModel.ReadAdvanceDefs.begin(),
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RAE = ProcModel.ReadAdvanceDefs.end(); RAI != RAE; ++RAI) {
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if (!(*RAI)->isSubClassOf("ReadAdvance"))
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@@ -884,7 +884,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
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if (!SCI->InstRWs.empty()) {
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// This class has a default ReadWrite list which can be overriden by
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// InstRW definitions.
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Record *RWDef = 0;
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Record *RWDef = nullptr;
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for (RecIter RWI = SCI->InstRWs.begin(), RWE = SCI->InstRWs.end();
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RWI != RWE; ++RWI) {
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Record *RWModelDef = (*RWI)->getValueAsDef("SchedModel");
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