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two register machineoperands are not identical unless their subregs match.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45455 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2007-12-30 20:55:08 +00:00
parent 9e3304900f
commit 0974d9a524
1 changed files with 2 additions and 1 deletions
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lib/CodeGen/MachineInstr.cpp
+2 -1
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@@ -153,7 +153,8 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
switch (getType()) {
default: assert(0 && "Unrecognized operand type");
case MachineOperand::MO_Register:
return getReg() == Other.getReg() && isDef() == Other.isDef();
return getReg() == Other.getReg() && isDef() == Other.isDef() &&
getSubReg() == Other.getSubReg();
case MachineOperand::MO_Immediate:
return getImm() == Other.getImm();
case MachineOperand::MO_MachineBasicBlock: