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Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171087 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-12-26 04:36:03 +00:00
parent 1fe132ae7d
commit 09a326d3f0
1 changed files with 20 additions and 32 deletions
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52
lib/Target/X86/X86InstrSSE.td
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@ -2679,40 +2679,28 @@ multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
} }
} // ExeDomain = SSEPackedInt } // ExeDomain = SSEPackedInt
multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
OpndItins itins, bit IsCommutable = 0> {
let Predicates = [HasAVX] in
defm VP#NAME# : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, v2i64,
VR128, memopv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
let Constraints = "$src1 = $dst" in
defm P#NAME# : PDI_binop_rm<opc, OpcodeStr, Opcode, v2i64, VR128, memopv2i64,
i128mem, itins, IsCommutable>;
let Predicates = [HasAVX2] in
defm VP#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, v4i64,
VR256, memopv4i64, i256mem, itins, IsCommutable,
0>, VEX_4V, VEX_L;
}
// These are ordered here for pattern ordering requirements with the fp versions // These are ordered here for pattern ordering requirements with the fp versions
let Predicates = [HasAVX] in { defm AND : PDI_binop_all<0xDB, "pand", and, SSE_BIT_ITINS_P, 1>;
defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64, defm OR : PDI_binop_all<0xEB, "por", or, SSE_BIT_ITINS_P, 1>;
i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V; defm XOR : PDI_binop_all<0xEF, "pxor", xor, SSE_BIT_ITINS_P, 1>;
defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64, defm ANDN : PDI_binop_all<0xDF, "pandn", X86andnp, SSE_BIT_ITINS_P, 0>;
i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
i128mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
}
let Constraints = "$src1 = $dst" in {
defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
i128mem, SSE_BIT_ITINS_P, 1>;
defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
i128mem, SSE_BIT_ITINS_P, 1>;
defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
i128mem, SSE_BIT_ITINS_P, 1>;
defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
i128mem, SSE_BIT_ITINS_P, 0>;
} // Constraints = "$src1 = $dst"
let Predicates = [HasAVX2] in {
defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V, VEX_L;
defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V, VEX_L;
defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V, VEX_L;
defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
i256mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V, VEX_L;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SSE 1 & 2 - Logical Instructions // SSE 1 & 2 - Logical Instructions