6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-22 10:29:35 +00:00
Code Issues Projects Releases Wiki Activity

Current definition of subtract with immediate instruction aliases uses CodeGenOnly defined instructions and post matcher expansion methods to emit real instructions add with immediate. However, they can directly alias add with immediate instruction and remove unnecessary definitions and code in MipsAsmParser.cpp. This patch makes no change in functionality, just removes unnecessary definitions and code.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206272 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vladimir Medic 2014-04-15 10:14:49 +00:00
parent bc4e3c024c
commit 09a79dc1a0
3 changed files with 14 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -906,10 +906,6 @@ bool MipsAsmParser::needsExpansion(MCInst &Inst) {
case Mips::LoadImm32Reg:
case Mips::LoadAddr32Imm:
case Mips::LoadAddr32Reg:
case Mips::SUBi:
case Mips::SUBiu:
case Mips::DSUBi:
case Mips::DSUBiu:
return true;
default:
return false;
@ -925,30 +921,6 @@ void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
return expandLoadAddressImm(Inst, IDLoc, Instructions);
case Mips::LoadAddr32Reg:
return expandLoadAddressReg(Inst, IDLoc, Instructions);
case Mips::SUBi:
Instructions.push_back(MCInstBuilder(Mips::ADDi)
.addReg(Inst.getOperand(0).getReg())
.addReg(Inst.getOperand(1).getReg())
.addImm(-Inst.getOperand(2).getImm()));
return;
case Mips::SUBiu:
Instructions.push_back(MCInstBuilder(Mips::ADDiu)
.addReg(Inst.getOperand(0).getReg())
.addReg(Inst.getOperand(1).getReg())
.addImm(-Inst.getOperand(2).getImm()));
return;
case Mips::DSUBi:
Instructions.push_back(MCInstBuilder(Mips::DADDi)
.addReg(Inst.getOperand(0).getReg())
.addReg(Inst.getOperand(1).getReg())
.addImm(-Inst.getOperand(2).getImm()));
return;
case Mips::DSUBiu:
Instructions.push_back(MCInstBuilder(Mips::DADDiu)
.addReg(Inst.getOperand(0).getReg())
.addReg(Inst.getOperand(1).getReg())
.addImm(-Inst.getOperand(2).getImm()));
return;
}
}

24
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -428,30 +428,14 @@ def : InstAlias<"add $rs, $imm",
def : InstAlias<"addu $rs, $imm",
(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
0>;
let isPseudo=1, usesCustomInserter=1, isCodeGenOnly=1 in {
def SUBi : MipsInst<(outs GPR32Opnd: $rt), (ins GPR32Opnd: $rs, simm16: $imm),
"sub\t$rt, $rs, $imm", [], II_DSUB, Pseudo>;
def SUBiu : MipsInst<(outs GPR32Opnd: $rt), (ins GPR32Opnd: $rs, simm16: $imm),
"subu\t$rt, $rs, $imm", [], II_DSUB, Pseudo>;
def DSUBi : MipsInst<(outs GPR64Opnd: $rt), (ins GPR64Opnd: $rs, simm16_64: $imm),
"ssub\t$rt, $rs, $imm", [], II_DSUB, Pseudo>;
def DSUBiu : MipsInst<(outs GPR64Opnd: $rt), (ins GPR64Opnd: $rs, simm16_64: $imm),
"ssubu\t$rt, $rs, $imm", [], II_DSUB, Pseudo>;
}
def : InstAlias<"dsubu $rt, $rs, $imm",
(DSUBiu GPR64Opnd:$rt, GPR64Opnd:$rs, simm16_64: $imm),
0>;
def : InstAlias<"sub $rs, $imm",
(SUBi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
0>;
def : InstAlias<"subu $rs, $imm",
(SUBiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
0>;
(DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
InvertedImOperand64: $imm),0>;
def : InstAlias<"dsub $rs, $imm",
(DSUBi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, InvertedImOperand64:$imm),
0>;
def : InstAlias<"dsubu $rs, $imm",
(DSUBiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, InvertedImOperand64:$imm),
0>;
/// Move between CPU and coprocessor registers

11
lib/Target/Mips/MipsInstrInfo.td
View File

@ -319,6 +319,10 @@ def InvertedImOperand : Operand<i32> {
let ParserMatchClass = MipsInvertedImmoperand;
}
def InvertedImOperand64 : Operand<i64> {
let ParserMatchClass = MipsInvertedImmoperand;
}
class mem_generic : Operand<iPTR> {
let PrintMethod = "printMemOperand";
let MIOperandInfo = (ops ptr_rc, simm16);
@ -1228,9 +1232,14 @@ def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : InstAlias<"sub, $rd, $rs, $imm",
(ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
def : InstAlias<"sub $rs, $imm",
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
0>;
def : InstAlias<"subu, $rd, $rs, $imm",
(ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
def : InstAlias<"subu $rs, $imm",
(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
0>;
//===----------------------------------------------------------------------===//
// Assembler Pseudo Instructions
//===----------------------------------------------------------------------===//