6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-25 13:24:46 +00:00
Code Issues Projects Releases Wiki Activity

Replace the tablegen RegisterClass field SubRegClassList with an alist-like data

Browse Source 
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2010-05-24 21:46:58 +00:00
parent 3946043a80
commit 09bc029865
13 changed files with 208 additions and 164 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
include/llvm/Target/Target.td
View File

@@ -125,9 +125,9 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
//
list<Register> MemberList = regList;
// SubClassList - Specify which register classes correspond to subregisters
// of this class. The order should be by subregister set index.
list<RegisterClass> SubRegClassList = [];
// SubRegClasses - Specify the register class of subregisters as a list of
// dags: (RegClass SubRegIndex, SubRegindex, ...)
list<dag> SubRegClasses = [];
// MethodProtos/MethodBodies - These members can be used to insert arbitrary
// code into a generated register class. The normal usage of this is to