mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-14 16:33:28 +00:00
Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73985 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
35d0e87937
commit
09c39fcf83
@ -751,6 +751,28 @@ class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsThumb, HasV5T];
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}
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// Thumb1 only
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class Thumb1I<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
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string asm, string cstr, list<dag> pattern>
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: InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asm;
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let Pattern = pattern;
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list<Predicate> Predicates = [IsThumb1Only];
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}
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class T1I<dag outs, dag ins, string asm, list<dag> pattern>
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: Thumb1I<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
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// Two-address instructions
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class T1It<dag outs, dag ins, string asm, list<dag> pattern>
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: Thumb1I<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
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class Thumb1Pat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsThumb1Only];
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}
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// T2I - Thumb2 instruction.
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class Thumb2I<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
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@ -278,111 +278,111 @@ def tPUSH : TI<(outs), (ins reglist:$src1, variable_ops),
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// Add with carry
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let isCommutable = 1 in
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def tADC : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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def tADC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"adc $dst, $rhs",
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[(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
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def tADDS : TI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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def tADDS : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"add $dst, $lhs, $rhs",
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[(set tGPR:$dst, (addc tGPR:$lhs, tGPR:$rhs))]>;
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def tADDi3 : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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def tADDi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"add $dst, $lhs, $rhs",
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[(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
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def tADDi8 : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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def tADDi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"add $dst, $rhs",
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[(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
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def tADDrr : TI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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def tADDrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"add $dst, $lhs, $rhs",
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[(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
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let neverHasSideEffects = 1 in
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def tADDhirr : TIt<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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def tADDhirr : T1It<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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"add $dst, $rhs @ addhirr", []>;
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def tADDrPCi : TI<(outs tGPR:$dst), (ins i32imm:$rhs),
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def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs),
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"add $dst, pc, $rhs * 4", []>;
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def tADDrSPi : TI<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs),
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def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs),
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"add $dst, $sp, $rhs * 4 @ addrspi", []>;
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def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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def tADDspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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"add $dst, $rhs * 4", []>;
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let isCommutable = 1 in
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def tAND : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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def tAND : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"and $dst, $rhs",
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[(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
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def tASRri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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def tASRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"asr $dst, $lhs, $rhs",
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[(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
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def tASRrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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def tASRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"asr $dst, $rhs",
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[(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
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def tBIC : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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def tBIC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"bic $dst, $rhs",
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[(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
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def tCMN : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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def tCMN : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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"cmn $lhs, $rhs",
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[(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
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def tCMPi8 : TI<(outs), (ins tGPR:$lhs, i32imm:$rhs),
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def tCMPi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
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def tCMPr : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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def tCMPr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
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def tTST : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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def tTST : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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"tst $lhs, $rhs",
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[(ARMcmpNZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
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def tCMNNZ : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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def tCMNNZ : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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"cmn $lhs, $rhs",
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[(ARMcmpNZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
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def tCMPNZi8 : TI<(outs), (ins tGPR:$lhs, i32imm:$rhs),
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def tCMPNZi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmpNZ tGPR:$lhs, imm0_255:$rhs)]>;
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def tCMPNZr : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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def tCMPNZr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmpNZ tGPR:$lhs, tGPR:$rhs)]>;
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// TODO: A7-37: CMP(3) - cmp hi regs
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let isCommutable = 1 in
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def tEOR : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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def tEOR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"eor $dst, $rhs",
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[(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
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def tLSLri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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def tLSLri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"lsl $dst, $lhs, $rhs",
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[(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
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def tLSLrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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def tLSLrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"lsl $dst, $rhs",
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[(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
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def tLSRri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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def tLSRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"lsr $dst, $lhs, $rhs",
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[(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
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def tLSRrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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def tLSRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"lsr $dst, $rhs",
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[(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
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// FIXME: This is not rematerializable because mov changes the condition code.
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def tMOVi8 : TI<(outs tGPR:$dst), (ins i32imm:$src),
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def tMOVi8 : T1I<(outs tGPR:$dst), (ins i32imm:$src),
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"mov $dst, $src",
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[(set tGPR:$dst, imm0_255:$src)]>;
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@ -392,41 +392,41 @@ def tMOVi8 : TI<(outs tGPR:$dst), (ins i32imm:$src),
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// Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
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// which is MOV(3). This also supports high registers.
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let neverHasSideEffects = 1 in {
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def tMOVr : TI<(outs tGPR:$dst), (ins tGPR:$src),
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def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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"cpy $dst, $src", []>;
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def tMOVhir2lor : TI<(outs tGPR:$dst), (ins GPR:$src),
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def tMOVhir2lor : T1I<(outs tGPR:$dst), (ins GPR:$src),
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"cpy $dst, $src\t@ hir2lor", []>;
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def tMOVlor2hir : TI<(outs GPR:$dst), (ins tGPR:$src),
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def tMOVlor2hir : T1I<(outs GPR:$dst), (ins tGPR:$src),
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"cpy $dst, $src\t@ lor2hir", []>;
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def tMOVhir2hir : TI<(outs GPR:$dst), (ins GPR:$src),
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def tMOVhir2hir : T1I<(outs GPR:$dst), (ins GPR:$src),
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"cpy $dst, $src\t@ hir2hir", []>;
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} // neverHasSideEffects
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let isCommutable = 1 in
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def tMUL : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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def tMUL : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"mul $dst, $rhs",
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[(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
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def tMVN : TI<(outs tGPR:$dst), (ins tGPR:$src),
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def tMVN : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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"mvn $dst, $src",
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[(set tGPR:$dst, (not tGPR:$src))]>;
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def tNEG : TI<(outs tGPR:$dst), (ins tGPR:$src),
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def tNEG : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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"neg $dst, $src",
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[(set tGPR:$dst, (ineg tGPR:$src))]>;
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let isCommutable = 1 in
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def tORR : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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def tORR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"orr $dst, $rhs",
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[(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
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def tREV : TI<(outs tGPR:$dst), (ins tGPR:$src),
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def tREV : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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"rev $dst, $src",
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[(set tGPR:$dst, (bswap tGPR:$src))]>,
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Requires<[IsThumb, HasV6]>;
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def tREV16 : TI<(outs tGPR:$dst), (ins tGPR:$src),
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def tREV16 : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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"rev16 $dst, $src",
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[(set tGPR:$dst,
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(or (and (srl tGPR:$src, (i32 8)), 0xFF),
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@ -435,7 +435,7 @@ def tREV16 : TI<(outs tGPR:$dst), (ins tGPR:$src),
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(and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
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Requires<[IsThumb, HasV6]>;
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def tREVSH : TI<(outs tGPR:$dst), (ins tGPR:$src),
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def tREVSH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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"revsh $dst, $src",
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[(set tGPR:$dst,
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(sext_inreg
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@ -443,53 +443,53 @@ def tREVSH : TI<(outs tGPR:$dst), (ins tGPR:$src),
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(shl tGPR:$src, (i32 8))), i16))]>,
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Requires<[IsThumb, HasV6]>;
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def tROR : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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def tROR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"ror $dst, $rhs",
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[(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
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// Subtract with carry
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def tSBC : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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def tSBC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"sbc $dst, $rhs",
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[(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
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def tSUBS : TI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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def tSUBS : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"sub $dst, $lhs, $rhs",
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[(set tGPR:$dst, (subc tGPR:$lhs, tGPR:$rhs))]>;
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// TODO: A7-96: STMIA - store multiple.
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def tSUBi3 : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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def tSUBi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"sub $dst, $lhs, $rhs",
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[(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
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def tSUBi8 : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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def tSUBi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"sub $dst, $rhs",
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[(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
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def tSUBrr : TI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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def tSUBrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"sub $dst, $lhs, $rhs",
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[(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
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def tSUBspi : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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def tSUBspi : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"sub $dst, $rhs * 4", []>;
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def tSXTB : TI<(outs tGPR:$dst), (ins tGPR:$src),
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def tSXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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"sxtb $dst, $src",
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[(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
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Requires<[IsThumb, HasV6]>;
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def tSXTH : TI<(outs tGPR:$dst), (ins tGPR:$src),
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def tSXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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"sxth $dst, $src",
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[(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
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Requires<[IsThumb, HasV6]>;
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def tUXTB : TI<(outs tGPR:$dst), (ins tGPR:$src),
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def tUXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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"uxtb $dst, $src",
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[(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
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Requires<[IsThumb, HasV6]>;
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def tUXTH : TI<(outs tGPR:$dst), (ins tGPR:$src),
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def tUXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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"uxth $dst, $src",
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[(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
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Requires<[IsThumb, HasV6]>;
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@ -562,9 +562,9 @@ def : ThumbPat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
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// Large immediate handling.
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// Two piece imms.
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def : ThumbPat<(i32 thumb_immshifted:$src),
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(tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
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(thumb_immshifted_shamt imm:$src))>;
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def : Thumb1Pat<(i32 thumb_immshifted:$src),
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(tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
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(thumb_immshifted_shamt imm:$src))>;
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def : ThumbPat<(i32 imm0_255_comp:$src),
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(tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
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def : Thumb1Pat<(i32 imm0_255_comp:$src),
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(tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
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